Initialze controller and log status
This commit is contained in:
parent
374c8322a0
commit
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GPG Key ID:
CA239FC6934E6F3A
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Cargo.lock
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||||||
|
name = "windows_x86_64_gnullvm"
|
||||||
|
version = "0.52.6"
|
||||||
|
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||||
|
checksum = "24d5b23dc417412679681396f2b49f3de8c1473deb516bd34410872eff51ed0d"
|
||||||
|
|
||||||
|
[[package]]
|
||||||
|
name = "windows_x86_64_msvc"
|
||||||
|
version = "0.52.6"
|
||||||
|
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||||
|
checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
|
||||||
|
|
||||||
|
[[package]]
|
||||||
|
name = "x86_64"
|
||||||
|
version = "0.15.1"
|
||||||
|
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||||
|
checksum = "4bc79523af8abf92fb1a970c3e086c5a343f6bcc1a0eb890f575cbb3b45743df"
|
||||||
|
dependencies = [
|
||||||
|
"bit_field",
|
||||||
|
"bitflags",
|
||||||
|
"rustversion",
|
||||||
|
"volatile",
|
||||||
|
]
|
||||||
@ -4,3 +4,6 @@ version = "0.1.0"
|
|||||||
edition = "2021"
|
edition = "2021"
|
||||||
|
|
||||||
[dependencies]
|
[dependencies]
|
||||||
|
bitflags = "2.6.0"
|
||||||
|
syslog_rpc = { version = "0.1.0", path = "../syslog/syslog_rpc" }
|
||||||
|
x86_64 = "0.15.1"
|
||||||
|
|||||||
282
src/main.rs
282
src/main.rs
@ -1,3 +1,281 @@
|
|||||||
fn main() {
|
use std::os::mikros::syscalls;
|
||||||
println!("Hello, world!");
|
|
||||||
|
use bitflags::{bitflags, Flags};
|
||||||
|
use x86_64::instructions::port::{Port, PortReadOnly, PortWriteOnly};
|
||||||
|
|
||||||
|
#[derive(Copy, Clone, Debug)]
|
||||||
|
enum Ps2Command {
|
||||||
|
ReadRAM(u8),
|
||||||
|
WriteRAM(u8, u8),
|
||||||
|
DisablePort2,
|
||||||
|
EnablePort2,
|
||||||
|
TestPort2,
|
||||||
|
TestController,
|
||||||
|
TestPort1,
|
||||||
|
DiagDump,
|
||||||
|
DisablePort1,
|
||||||
|
EnablePort1,
|
||||||
|
ReadControllerInput,
|
||||||
|
CopyInputLowStatus,
|
||||||
|
CopyInputHighStatus,
|
||||||
|
ReadControllerOutput,
|
||||||
|
WriteControllerOutput(u8),
|
||||||
|
WritePort1Output(u8),
|
||||||
|
WritePort2Output(u8),
|
||||||
|
WritePort2Input(u8),
|
||||||
|
PulseOutput(u8),
|
||||||
|
WritePort1Input(u8),
|
||||||
|
}
|
||||||
|
|
||||||
|
impl Ps2Command {
|
||||||
|
fn get_command_byte(self) -> Option<u8> {
|
||||||
|
match self {
|
||||||
|
Self::ReadRAM(addr) => Some(0x20 + (addr & 0x1F)),
|
||||||
|
Self::WriteRAM(addr, _) => Some(0x60 + (addr & 0x1F)),
|
||||||
|
Self::DisablePort2 => Some(0xA7),
|
||||||
|
Self::EnablePort2 => Some(0xA8),
|
||||||
|
Self::TestPort2 => Some(0xA9),
|
||||||
|
Self::TestController => Some(0xAA),
|
||||||
|
Self::TestPort1 => Some(0xAB),
|
||||||
|
Self::DiagDump => Some(0xAC),
|
||||||
|
Self::DisablePort1 => Some(0xAD),
|
||||||
|
Self::EnablePort1 => Some(0xAE),
|
||||||
|
Self::ReadControllerInput => Some(0xC0),
|
||||||
|
Self::CopyInputLowStatus => Some(0xC1),
|
||||||
|
Self::CopyInputHighStatus => Some(0xC2),
|
||||||
|
Self::ReadControllerOutput => Some(0xD0),
|
||||||
|
Self::WriteControllerOutput(_) => Some(0xD1),
|
||||||
|
Self::WritePort1Output(_) => Some(0xD2),
|
||||||
|
Self::WritePort2Output(_) => Some(0xD3),
|
||||||
|
Self::WritePort2Input(_) => Some(0xD4),
|
||||||
|
Self::PulseOutput(mask) => Some(0xF0 + (mask & 0xF)),
|
||||||
|
Self::WritePort1Input(_) => None,
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
fn get_data_byte(self) -> Option<u8> {
|
||||||
|
match self {
|
||||||
|
Self::WriteRAM(_, data) => Some(data),
|
||||||
|
Self::WriteControllerOutput(data) => Some(data),
|
||||||
|
Self::WritePort1Output(data) => Some(data),
|
||||||
|
Self::WritePort2Output(data) => Some(data),
|
||||||
|
Self::WritePort2Input(data) => Some(data),
|
||||||
|
Self::WritePort1Input(data) => Some(data),
|
||||||
|
_ => None,
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
fn has_data_response(self) -> bool {
|
||||||
|
matches!(
|
||||||
|
self,
|
||||||
|
Self::ReadRAM(_)
|
||||||
|
| Self::TestPort2
|
||||||
|
| Self::TestController
|
||||||
|
| Self::TestPort1
|
||||||
|
| Self::ReadControllerInput
|
||||||
|
| Self::ReadControllerOutput
|
||||||
|
)
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
bitflags! {
|
||||||
|
#[derive(Clone, Copy, Debug)]
|
||||||
|
pub struct Ps2Status: u8 {
|
||||||
|
const OutputBufFull = 0b0000_0001;
|
||||||
|
const InputBufFull = 0b0000_0010;
|
||||||
|
const SystemFlag = 0b0000_0100;
|
||||||
|
const CommandData = 0b0000_1000;
|
||||||
|
const Bit4 = 0b0001_0000;
|
||||||
|
const Bit5 = 0b0010_0000;
|
||||||
|
const TimeoutError = 0b0100_0000;
|
||||||
|
const ParityError = 0b1000_0000;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
bitflags! {
|
||||||
|
#[derive(Clone, Copy, Debug)]
|
||||||
|
pub struct Ps2OutputPort: u8 {
|
||||||
|
const SystemReset = 0b0000_0001;
|
||||||
|
const A20Gate = 0b0000_0010;
|
||||||
|
const Port2Clock = 0b0000_0100;
|
||||||
|
const Port2Data = 0b0000_1000;
|
||||||
|
const OutputBufFullPort1 = 0b0001_0000;
|
||||||
|
const OutputBufFullPort2 = 0b0010_0000;
|
||||||
|
const Port1Clock = 0b0100_0000;
|
||||||
|
const Port12Data = 0b1000_0000;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
bitflags! {
|
||||||
|
#[derive(Clone, Copy, Debug)]
|
||||||
|
pub struct Ps2ConfigByte: u8 {
|
||||||
|
const Port1Interrupt = 0b0000_0001;
|
||||||
|
const Port2Interrupt = 0b0000_0010;
|
||||||
|
const SystemFlag = 0b0000_0100;
|
||||||
|
const ShouldZero = 0b0000_1000;
|
||||||
|
const Port1ClockDisable = 0b0001_0000;
|
||||||
|
const Port2ClockDisable = 0b0010_0000;
|
||||||
|
const Port1Translation = 0b0100_0000;
|
||||||
|
const MustZero = 0b1000_0000;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
struct Ps2Controller {
|
||||||
|
data_port: Port<u8>,
|
||||||
|
status_register: PortReadOnly<u8>,
|
||||||
|
command_register: PortWriteOnly<u8>,
|
||||||
|
two_ports: bool,
|
||||||
|
port1_ok: bool,
|
||||||
|
port2_ok: bool,
|
||||||
|
}
|
||||||
|
|
||||||
|
#[derive(Clone, Copy, Debug)]
|
||||||
|
enum Ps2InitFailure {
|
||||||
|
SelfTestFailed,
|
||||||
|
}
|
||||||
|
|
||||||
|
impl Ps2Controller {
|
||||||
|
pub unsafe fn new(base: u16) -> Self {
|
||||||
|
Self {
|
||||||
|
data_port: Port::new(base),
|
||||||
|
status_register: PortReadOnly::new(base + 0x4),
|
||||||
|
command_register: PortWriteOnly::new(base + 0x4),
|
||||||
|
two_ports: false, // This is determined during initialiation
|
||||||
|
port1_ok: false, // This is determined during initialiation
|
||||||
|
port2_ok: false, // This is determined during initialiation
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
fn get_status(&mut self) -> Ps2Status {
|
||||||
|
Ps2Status::from_bits(unsafe { self.status_register.read() }).unwrap()
|
||||||
|
}
|
||||||
|
|
||||||
|
fn send_command(&mut self, command: Ps2Command) -> Option<u8> {
|
||||||
|
if let Some(command_byte) = command.get_command_byte() {
|
||||||
|
while self.get_status().contains(Ps2Status::InputBufFull) {}
|
||||||
|
unsafe { self.command_register.write(command_byte) }
|
||||||
|
}
|
||||||
|
if let Some(data_byte) = command.get_data_byte() {
|
||||||
|
while self.get_status().contains(Ps2Status::InputBufFull) {}
|
||||||
|
unsafe { self.data_port.write(data_byte) }
|
||||||
|
}
|
||||||
|
if command.has_data_response() {
|
||||||
|
while !self.get_status().contains(Ps2Status::OutputBufFull) {}
|
||||||
|
Some(unsafe { self.data_port.read() })
|
||||||
|
} else {
|
||||||
|
None
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
fn get_config_byte(&mut self) -> Ps2ConfigByte {
|
||||||
|
let config_byte = self.send_command(Ps2Command::ReadRAM(0)).unwrap();
|
||||||
|
Ps2ConfigByte::from_bits(config_byte).unwrap()
|
||||||
|
}
|
||||||
|
|
||||||
|
fn set_config_byte(&mut self, config_byte: Ps2ConfigByte) {
|
||||||
|
self.send_command(Ps2Command::WriteRAM(0, config_byte.bits()));
|
||||||
|
}
|
||||||
|
|
||||||
|
fn initialize(&mut self) -> Result<(), Ps2InitFailure> {
|
||||||
|
self.send_command(Ps2Command::DisablePort1);
|
||||||
|
self.send_command(Ps2Command::DisablePort2);
|
||||||
|
|
||||||
|
// Flush the output buffer
|
||||||
|
unsafe { self.data_port.read() };
|
||||||
|
|
||||||
|
let mut config_byte = self.get_config_byte();
|
||||||
|
config_byte.set(Ps2ConfigByte::Port1Interrupt, false);
|
||||||
|
config_byte.set(Ps2ConfigByte::Port1ClockDisable, false);
|
||||||
|
config_byte.set(Ps2ConfigByte::Port1Translation, false);
|
||||||
|
self.set_config_byte(config_byte);
|
||||||
|
|
||||||
|
let self_test_result = self.send_command(Ps2Command::TestController).unwrap();
|
||||||
|
if self_test_result != 0x55 {
|
||||||
|
return Err(Ps2InitFailure::SelfTestFailed);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Testing the controller can reset it, so redo early initialization to be safe.
|
||||||
|
self.send_command(Ps2Command::DisablePort1);
|
||||||
|
self.send_command(Ps2Command::DisablePort2);
|
||||||
|
|
||||||
|
// Flush the output buffer
|
||||||
|
unsafe { self.data_port.read() };
|
||||||
|
|
||||||
|
self.set_config_byte(config_byte);
|
||||||
|
|
||||||
|
self.send_command(Ps2Command::EnablePort2);
|
||||||
|
if !self
|
||||||
|
.get_config_byte()
|
||||||
|
.contains(Ps2ConfigByte::Port2ClockDisable)
|
||||||
|
{
|
||||||
|
self.two_ports = true;
|
||||||
|
self.send_command(Ps2Command::DisablePort2);
|
||||||
|
let mut config_byte = self.get_config_byte();
|
||||||
|
config_byte.set(Ps2ConfigByte::Port2Interrupt, false);
|
||||||
|
config_byte.set(Ps2ConfigByte::Port2ClockDisable, false);
|
||||||
|
self.set_config_byte(config_byte);
|
||||||
|
}
|
||||||
|
|
||||||
|
let port1_test_result = self.send_command(Ps2Command::TestPort1).unwrap();
|
||||||
|
if port1_test_result == 0x0 {
|
||||||
|
self.port1_ok = true;
|
||||||
|
self.send_command(Ps2Command::EnablePort1);
|
||||||
|
}
|
||||||
|
|
||||||
|
if self.two_ports {
|
||||||
|
let port2_test_result = self.send_command(Ps2Command::TestPort2).unwrap();
|
||||||
|
if port2_test_result == 0x0 {
|
||||||
|
self.port2_ok = true;
|
||||||
|
self.send_command(Ps2Command::EnablePort2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
Ok(())
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
fn main() {
|
||||||
|
let syslog_pid = loop {
|
||||||
|
if let Some(pid) = syscalls::try_get_registered(2) {
|
||||||
|
break pid;
|
||||||
|
}
|
||||||
|
};
|
||||||
|
let syslog_client = syslog_rpc::Client::new(syslog_pid);
|
||||||
|
syslog_client
|
||||||
|
.send_text_message("ps2", "Initializing controller")
|
||||||
|
.unwrap();
|
||||||
|
let mut controller = unsafe { Ps2Controller::new(0x60) };
|
||||||
|
if controller.initialize().is_err() {
|
||||||
|
syslog_client
|
||||||
|
.send_text_message("ps2", "Controller initialization failed, aborting")
|
||||||
|
.unwrap();
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if controller.two_ports {
|
||||||
|
syslog_client
|
||||||
|
.send_text_message("ps2", "Controller has two ports")
|
||||||
|
.unwrap();
|
||||||
|
} else {
|
||||||
|
syslog_client
|
||||||
|
.send_text_message("ps2", "Controller has one port")
|
||||||
|
.unwrap();
|
||||||
|
}
|
||||||
|
|
||||||
|
if controller.port1_ok {
|
||||||
|
syslog_client.send_text_message("ps2", "Port 1 OK").unwrap();
|
||||||
|
} else {
|
||||||
|
syslog_client
|
||||||
|
.send_text_message("ps2", "Port 1 failed self test")
|
||||||
|
.unwrap();
|
||||||
|
}
|
||||||
|
|
||||||
|
if controller.two_ports {
|
||||||
|
if controller.port2_ok {
|
||||||
|
syslog_client.send_text_message("ps2", "Port 1 OK").unwrap();
|
||||||
|
} else {
|
||||||
|
syslog_client
|
||||||
|
.send_text_message("ps2", "Port 1 failed self test")
|
||||||
|
.unwrap();
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user