Switch to pci_types for header parsing
This commit is contained in:
parent
465a46f294
commit
d18ead3093
GPG Key ID:
7B5F6AFBEC7EE78E
194
Cargo.lock
generated
194
Cargo.lock
generated
@ -1,6 +1,6 @@
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# This file is automatically @generated by Cargo.
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# It is not intended for manual editing.
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version = 3
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version = 4
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[[package]]
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name = "atomic-polyfill"
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@ -47,9 +47,9 @@ checksum = "dc827186963e592360843fb5ba4b973e145841266c1357f7180c43526f2e5b61"
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[[package]]
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@ -71,9 +71,9 @@ checksum = "67ba02a97a2bd10f4b59b25c7973101c79642302776489e030cd13cdab09ed15"
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[[package]]
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@ -88,9 +88,9 @@ dependencies = [
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[[package]]
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@ -106,9 +106,9 @@ checksum = "edd0f118536f44f5ccd48bcb8b111bdc3de888b58c74639dfb034a357d0f206d"
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[[package]]
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@ -121,9 +121,9 @@ dependencies = [
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[[package]]
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[[package]]
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@ -141,9 +141,9 @@ dependencies = [
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[[package]]
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"hashbrown",
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@ -151,9 +151,9 @@ dependencies = [
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[[package]]
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[[package]]
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@ -171,6 +171,22 @@ version = "2.7.4"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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[[package]]
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@ -200,7 +216,9 @@ version = "0.1.0"
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"binread",
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"derive-try-from-primitive",
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"pci-ids",
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"pci_rpc",
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"pci_types",
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"serde",
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"spin",
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"syslog_rpc",
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@ -208,6 +226,19 @@ dependencies = [
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"x86_64",
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]
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[[package]]
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"nom",
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"proc-macro2",
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"quote",
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]
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[[package]]
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@ -217,10 +248,58 @@ dependencies = [
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]
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[[package]]
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[[package]]
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"phf_generator",
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"phf_shared",
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[[package]]
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dependencies = [
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"phf_shared",
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"rand",
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[[package]]
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dependencies = [
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[[package]]
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dependencies = [
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"cobs",
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"embedded-io 0.4.0",
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@ -231,27 +310,42 @@ dependencies = [
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[[package]]
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[[package]]
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@ -267,9 +361,9 @@ dependencies = [
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[[package]]
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@ -279,24 +373,24 @@ checksum = "94143f37725109f92c262ed2cf5e59bce7498c01bcc1502d7b9afe439a4e9f49"
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[[package]]
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@ -309,10 +403,16 @@ dependencies = [
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]
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[[package]]
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[[package]]
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@ -342,9 +442,9 @@ dependencies = [
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[[package]]
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@ -369,9 +469,9 @@ dependencies = [
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[[package]]
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@ -390,9 +490,9 @@ dependencies = [
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@ -403,9 +503,9 @@ dependencies = [
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[[package]]
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@ -479,18 +579,18 @@ checksum = "589f6da84c646204747d1270a2a5661ea66ed1cced2631d546fdfb155959f9ec"
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|
||||
checksum = "4bc79523af8abf92fb1a970c3e086c5a343f6bcc1a0eb890f575cbb3b45743df"
|
||||
checksum = "0f042214de98141e9c8706e8192b73f56494087cc55ebec28ce10f26c5c364ae"
|
||||
dependencies = [
|
||||
"bit_field",
|
||||
"bitflags",
|
||||
|
||||
@ -6,7 +6,9 @@ edition = "2021"
|
||||
[dependencies]
|
||||
binread = "2.2.0"
|
||||
derive-try-from-primitive = "1.0.0"
|
||||
pci-ids = "0.2.5"
|
||||
pci_rpc = { version = "0.1.0", path = "pci_rpc" }
|
||||
pci_types = "0.10.0"
|
||||
serde = { path = "../serde/serde", features = ["derive"] }
|
||||
spin = "0.9.8"
|
||||
syslog_rpc = { version = "0.1.0", path = "../syslog/syslog_rpc" }
|
||||
|
||||
576
src/main.rs
576
src/main.rs
@ -1,11 +1,18 @@
|
||||
#![allow(clippy::verbose_bit_mask)]
|
||||
use std::{
|
||||
collections::HashMap, fs, io::Cursor, os::mikros::{ipc, syscalls}, path::{Path, PathBuf}
|
||||
collections::HashMap,
|
||||
fs,
|
||||
os::mikros::{ipc, syscalls},
|
||||
path::{Path, PathBuf},
|
||||
};
|
||||
|
||||
use binread::prelude::*;
|
||||
use device_types::{Class, InvalidClass};
|
||||
use device_types::Class;
|
||||
use pci_ids::Device;
|
||||
use pci_rpc::Server;
|
||||
use pci_types::{
|
||||
capability::PciCapability,
|
||||
Bar, ConfigRegionAccess, EndpointHeader, PciAddress, PciHeader, MAX_BARS,
|
||||
};
|
||||
use serde::{Deserialize, Serialize};
|
||||
use spin::Mutex;
|
||||
use x86_64::instructions::port::{Port, PortWriteOnly};
|
||||
@ -15,217 +22,36 @@ pub mod device_types;
|
||||
static CONFIG_PORT: Mutex<PortWriteOnly<u32>> = Mutex::new(PortWriteOnly::new(0xCF8));
|
||||
static DATA_PORT: Mutex<Port<u32>> = Mutex::new(Port::new(0xCFC));
|
||||
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
struct ConfigAccessor(u32);
|
||||
struct PortAccessor;
|
||||
|
||||
impl ConfigAccessor {
|
||||
pub fn new(bus: u8, device: u8, function: u8) -> Self {
|
||||
assert!(device < 32);
|
||||
assert!(function < 8);
|
||||
Self(
|
||||
(u32::from(bus) << 16)
|
||||
| (u32::from(device) << 11)
|
||||
| (u32::from(function) << 8)
|
||||
| 0x8000_0000,
|
||||
)
|
||||
}
|
||||
|
||||
fn read(self, index: u8) -> u32 {
|
||||
assert!(index < 64);
|
||||
let register = index * 4;
|
||||
unsafe { CONFIG_PORT.lock().write(self.0 | u32::from(register)) }
|
||||
impl ConfigRegionAccess for PortAccessor {
|
||||
unsafe fn read(&self, address: pci_types::PciAddress, offset: u16) -> u32 {
|
||||
unsafe {
|
||||
CONFIG_PORT.lock().write(
|
||||
0x8000_0000
|
||||
| (u32::from(address.bus()) << 16)
|
||||
| (u32::from(address.device()) << 11)
|
||||
| (u32::from(address.function()) << 8)
|
||||
| u32::from(offset),
|
||||
)
|
||||
}
|
||||
|
||||
unsafe { DATA_PORT.lock().read() }
|
||||
}
|
||||
|
||||
fn write(self, index: u8, data: u32) {
|
||||
assert!(index < 64);
|
||||
let register = index * 4;
|
||||
unsafe { CONFIG_PORT.lock().write(self.0 | u32::from(register)) }
|
||||
|
||||
unsafe { DATA_PORT.lock().write(data) }
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
pub struct InvalidHeaderType;
|
||||
|
||||
#[derive(Debug)]
|
||||
pub struct ConfigRaw {
|
||||
pub data: [u8; 256],
|
||||
}
|
||||
|
||||
impl ConfigRaw {
|
||||
pub fn new(bus: u8, device: u8, function: u8) -> Self {
|
||||
let accessor = ConfigAccessor::new(bus, device, function);
|
||||
let mut data = [0; 256];
|
||||
for reg_num in 0..32 {
|
||||
let reg = accessor.read(reg_num);
|
||||
for (i, &byte) in reg.to_le_bytes().iter().enumerate() {
|
||||
data[usize::from(reg_num) * 4 + i] = byte;
|
||||
}
|
||||
unsafe fn write(&self, address: pci_types::PciAddress, offset: u16, value: u32) {
|
||||
unsafe {
|
||||
CONFIG_PORT.lock().write(
|
||||
0x8000_0000
|
||||
| (u32::from(address.bus()) << 16)
|
||||
| (u32::from(address.device()) << 11)
|
||||
| (u32::from(address.function()) << 8)
|
||||
| u32::from(offset),
|
||||
)
|
||||
}
|
||||
ConfigRaw { data }
|
||||
|
||||
unsafe { DATA_PORT.lock().write(value) }
|
||||
}
|
||||
|
||||
pub fn common(&self) -> ConfigCommon {
|
||||
Cursor::new(&self.data)
|
||||
.read_le()
|
||||
.expect("Unable to parse PCI device common config")
|
||||
}
|
||||
|
||||
pub fn config(&self) -> Result<ConfigTypeSpecific, InvalidHeaderType> {
|
||||
match Cursor::new(&self.data).read_le() {
|
||||
Ok(cfg) => Ok(cfg),
|
||||
Err(binread::Error::NoVariantMatch { pos: _ }) => Err(InvalidHeaderType),
|
||||
Err(err) => panic!("Only NoVariantMatch should be possible: {:?}", err),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone, BinRead)]
|
||||
#[repr(C)]
|
||||
pub struct ConfigCommon {
|
||||
pub vendor_id: u16,
|
||||
pub device_id: u16,
|
||||
pub command: u16,
|
||||
pub status: u16,
|
||||
pub rev_id: u8,
|
||||
pub prog_if: u8,
|
||||
pub subclass: u8,
|
||||
pub class_code: u8,
|
||||
pub cache_line_size: u8,
|
||||
pub lat_timer: u8,
|
||||
pub header_type: u8,
|
||||
pub bist: u8,
|
||||
}
|
||||
|
||||
impl ConfigCommon {
|
||||
fn class(&self) -> Result<Class, InvalidClass> {
|
||||
Class::new(self.class_code, self.subclass, self.prog_if)
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone, BinRead)]
|
||||
pub enum ConfigTypeSpecific {
|
||||
Type0(ConfigType0),
|
||||
Type1(ConfigType1),
|
||||
Type2(ConfigType2),
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone, BinRead)]
|
||||
#[repr(C)]
|
||||
pub struct ConfigType0 {
|
||||
pub vendor_id: u16,
|
||||
pub device_id: u16,
|
||||
pub command: u16,
|
||||
pub status: u16,
|
||||
pub rev_id: u8,
|
||||
pub prog_if: u8,
|
||||
pub subclass: u8,
|
||||
pub class_code: u8,
|
||||
pub cache_line_size: u8,
|
||||
pub lat_timer: u8,
|
||||
#[br(assert(header_type & 0x7F == 0))]
|
||||
pub header_type: u8,
|
||||
pub bist: u8,
|
||||
pub bars: [u32; 6],
|
||||
pub cardbus_cis: u32,
|
||||
pub sub_sys_vendor_id: u16,
|
||||
pub sub_sys_id: u16,
|
||||
pub exp_rom_base: u32,
|
||||
pub cap_ptr: u8,
|
||||
reserved: [u8; 7],
|
||||
pub int_line: u8,
|
||||
pub int_pin: u8,
|
||||
pub min_grant: u8,
|
||||
pub max_latency: u8,
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone, BinRead)]
|
||||
#[repr(C)]
|
||||
pub struct ConfigType1 {
|
||||
pub vendor_id: u16,
|
||||
pub device_id: u16,
|
||||
pub command: u16,
|
||||
pub status: u16,
|
||||
pub rev_id: u8,
|
||||
pub prog_if: u8,
|
||||
pub subclass: u8,
|
||||
pub class_code: u8,
|
||||
pub cache_line_size: u8,
|
||||
pub lat_timer: u8,
|
||||
#[br(assert(header_type & 0x7F == 1))]
|
||||
pub header_type: u8,
|
||||
pub bist: u8,
|
||||
pub bars: [u32; 2],
|
||||
pub prim_bus_num: u8,
|
||||
pub sec_bus_num: u8,
|
||||
pub sub_bus_num: u8,
|
||||
pub sec_latency_timer: u8,
|
||||
pub io_base: u8,
|
||||
pub io_limit: u8,
|
||||
pub sec_status: u16,
|
||||
pub mem_base: u16,
|
||||
pub mem_limit: u16,
|
||||
pub prefetch_mem_base: u16,
|
||||
pub prefetch_mem_limit: u16,
|
||||
pub prefetch_mem_base_upper32: u32,
|
||||
pub prefetch_mem_limit_upper32: u32,
|
||||
pub io_base_upper16: u16,
|
||||
pub io_limit_upper16: u16,
|
||||
pub cap_ptr: u8,
|
||||
reserved: [u8; 3],
|
||||
pub exp_rom_base: u32,
|
||||
pub int_line: u8,
|
||||
pub int_pin: u8,
|
||||
pub bridge_control: u16,
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone, BinRead)]
|
||||
#[repr(C)]
|
||||
#[repr(packed)]
|
||||
pub struct ConfigType2 {
|
||||
pub vendor_id: u16,
|
||||
pub device_id: u16,
|
||||
pub command: u16,
|
||||
pub status: u16,
|
||||
pub rev_id: u8,
|
||||
pub prog_if: u8,
|
||||
pub subclass: u8,
|
||||
pub class_code: u8,
|
||||
pub cache_line_size: u8,
|
||||
pub lat_timer: u8,
|
||||
#[br(assert(header_type & 0x7F == 2))]
|
||||
pub header_type: u8,
|
||||
pub bist: u8,
|
||||
pub cap_ptr: u8,
|
||||
reserved: u8,
|
||||
pub sec_status: u16,
|
||||
pub mem_base_0: u32,
|
||||
pub mem_limit_0: u32,
|
||||
pub mem_base_1: u32,
|
||||
pub mem_limit_1: u32,
|
||||
pub io_base_0: u32,
|
||||
pub io_limit_0: u32,
|
||||
pub io_base_1: u32,
|
||||
pub io_limit_1: u32,
|
||||
pub int_line: u8,
|
||||
pub int_pin: u8,
|
||||
pub bridge_control: u16,
|
||||
pub sub_sys_vendor_id: u16,
|
||||
pub sub_sys_id: u16,
|
||||
pub legacy_card_base: u32,
|
||||
}
|
||||
|
||||
#[derive(Debug, Clone)]
|
||||
pub struct Device {
|
||||
pub bus: u8,
|
||||
pub device: u8,
|
||||
pub function: u8,
|
||||
pub common: ConfigCommon,
|
||||
pub type_specific: ConfigTypeSpecific,
|
||||
pub class: Class,
|
||||
}
|
||||
|
||||
#[derive(Serialize, Deserialize, Debug)]
|
||||
@ -257,91 +83,73 @@ impl DriverMapping {
|
||||
}
|
||||
}
|
||||
|
||||
fn scan_bus(bus: u8, device_vec: &mut Vec<Device>) {
|
||||
fn scan_bus(bus: u8, device_vec: &mut Vec<PciAddress>) {
|
||||
for device in 0..32 {
|
||||
scan_device(bus, device, device_vec);
|
||||
}
|
||||
}
|
||||
|
||||
fn scan_device(bus: u8, device: u8, device_vec: &mut Vec<Device>) {
|
||||
let func0cfg = ConfigRaw::new(bus, device, 0);
|
||||
if func0cfg.common().vendor_id == 0xFFFF {
|
||||
fn scan_device(bus: u8, device: u8, device_vec: &mut Vec<PciAddress>) {
|
||||
//let func0cfg = ConfigRaw::new(bus, device, 0);
|
||||
let func0cfg = PciHeader::new(PciAddress::new(0, bus, device, 0));
|
||||
if func0cfg.id(PortAccessor).0 == 0xFFFF {
|
||||
return;
|
||||
}
|
||||
let header_type = func0cfg.common().header_type;
|
||||
found_function(bus, device, 0, &func0cfg, device_vec);
|
||||
if (header_type & 0x80) != 0 {
|
||||
device_vec.push(PciAddress::new(0, bus, device, 0));
|
||||
if func0cfg.has_multiple_functions(PortAccessor) {
|
||||
for func in 1..8 {
|
||||
let cfg = ConfigRaw::new(bus, device, func);
|
||||
if cfg.common().vendor_id != 0xFFFF {
|
||||
found_function(bus, device, func, &cfg, device_vec);
|
||||
let adresss = PciAddress::new(0, bus, device, func);
|
||||
let cfg = PciHeader::new(adresss);
|
||||
if cfg.id(PortAccessor).0 != 0xFFFF {
|
||||
device_vec.push(adresss)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn found_function(
|
||||
bus: u8,
|
||||
device: u8,
|
||||
function: u8,
|
||||
cfg: &ConfigRaw,
|
||||
device_vec: &mut Vec<Device>,
|
||||
) {
|
||||
let type_specific = if let Ok(type_specific) = cfg.config() {
|
||||
type_specific
|
||||
} else {
|
||||
return;
|
||||
};
|
||||
let class = if let Ok(class) = cfg.common().class() {
|
||||
class
|
||||
} else {
|
||||
return;
|
||||
};
|
||||
let device = Device {
|
||||
bus,
|
||||
device,
|
||||
function,
|
||||
common: cfg.common(),
|
||||
type_specific,
|
||||
class,
|
||||
};
|
||||
device_vec.push(device);
|
||||
}
|
||||
|
||||
struct PCIServer(Vec<Device>);
|
||||
struct PCIServer(Vec<PciAddress>);
|
||||
|
||||
impl Server for PCIServer {
|
||||
fn get_bars(&self, bus: u8, dev_no: u8, func: u8) -> Result<[(bool, u32, u32); 6], ()> {
|
||||
let device = self
|
||||
let address = *self
|
||||
.0
|
||||
.iter()
|
||||
.find(|dev| dev.bus == bus && dev.device == dev_no && dev.function == func)
|
||||
.find(|addr| addr.bus() == bus && addr.device() == dev_no && addr.function() == func)
|
||||
.ok_or(())?;
|
||||
match device.type_specific {
|
||||
ConfigTypeSpecific::Type0(hdr) => {
|
||||
let accessor = ConfigAccessor::new(bus, dev_no, func);
|
||||
let mut res: [(bool, u32, u32); 6] = [(false, 0, 0); 6];
|
||||
for (i, bar) in hdr.bars.iter().copied().enumerate() {
|
||||
let bar_idx = (i + 0x4) as u8;
|
||||
accessor.write(bar_idx, 0xFFFF_FFFF);
|
||||
let bar_tmp = accessor.read(bar_idx);
|
||||
let info_bits = if bar & 0x1 == 1 {
|
||||
bar_tmp & !0x3
|
||||
} else {
|
||||
bar_tmp & !0xF
|
||||
};
|
||||
let size = !(info_bits) + 1;
|
||||
accessor.write(bar_idx, bar);
|
||||
if bar & 0x1 == 1 {
|
||||
res[i] = (true, bar & !0x3, size);
|
||||
} else {
|
||||
res[i] = (false, bar & !0xF, size);
|
||||
};
|
||||
let common_hdr = PciHeader::new(address);
|
||||
if let Some(hdr) = EndpointHeader::from_header(common_hdr, PortAccessor) {
|
||||
let mut res: [(bool, u32, u32); 6] = [(false, 0, 0); 6];
|
||||
let mut i = 0;
|
||||
while i < MAX_BARS as u8 {
|
||||
let Some(bar) = hdr.bar(i, PortAccessor) else {
|
||||
i += 1;
|
||||
continue;
|
||||
};
|
||||
match bar {
|
||||
Bar::Memory32 {
|
||||
address,
|
||||
size,
|
||||
prefetchable: _,
|
||||
} => {
|
||||
res[i as usize] = (false, address, size);
|
||||
}
|
||||
Bar::Memory64 {
|
||||
address: _,
|
||||
size: _,
|
||||
prefetchable: _,
|
||||
} => {
|
||||
i += 1;
|
||||
// TODO
|
||||
}
|
||||
Bar::Io { port } => {
|
||||
res[i as usize] = (true, port, 0);
|
||||
}
|
||||
}
|
||||
Ok(res)
|
||||
i += 1;
|
||||
}
|
||||
ConfigTypeSpecific::Type1(_) => Err(()),
|
||||
ConfigTypeSpecific::Type2(_) => Err(()),
|
||||
Ok(res)
|
||||
} else {
|
||||
Err(())
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -355,65 +163,209 @@ fn main() {
|
||||
}
|
||||
};
|
||||
let syslog_client = syslog_rpc::Client::new(syslog_pid);
|
||||
let mut device_vec = Vec::new();
|
||||
scan_bus(0, &mut device_vec);
|
||||
let srv = PCIServer(device_vec.clone());
|
||||
let mut device_addresses = Vec::new();
|
||||
scan_bus(0, &mut device_addresses);
|
||||
let srv = PCIServer(device_addresses.clone());
|
||||
pci_rpc::register_server(Box::new(srv));
|
||||
let mut driver_map: HashMap<PathBuf, Vec<(u8, u8, u8)>> = HashMap::new();
|
||||
for device in &device_vec {
|
||||
for &address in &device_addresses {
|
||||
let common_hdr = PciHeader::new(address);
|
||||
let (vid, pid) = common_hdr.id(PortAccessor);
|
||||
let device_id = Device::from_vid_pid(vid, pid);
|
||||
let (_, class, subclass, progif) = common_hdr.revision_and_class(PortAccessor);
|
||||
let Ok(class) = Class::new(class, subclass, progif) else {
|
||||
continue;
|
||||
};
|
||||
syslog_client.send_text_message(
|
||||
"pci",
|
||||
format!(
|
||||
"Bus {}, device {}, function {}: Type {:?}, Vendor ID {:#x}, Device ID {:#x}, Header type {}",
|
||||
device.bus,
|
||||
device.device,
|
||||
device.function,
|
||||
device.class,
|
||||
device.common.vendor_id,
|
||||
device.common.device_id,
|
||||
device.common.header_type,
|
||||
"Bus {}, device {}, function {}: Type {:?}, Vendor ID {:#x} ({}), Device ID {:#x} ({}), Header type {:?}",
|
||||
address.bus(),
|
||||
address.device(),
|
||||
address.function(),
|
||||
class,
|
||||
vid,
|
||||
device_id.map_or("Unknown", |x| x.vendor().name()),
|
||||
pid,
|
||||
device_id.map_or("Unknown", |x| x.name()),
|
||||
common_hdr.header_type(PortAccessor),
|
||||
)
|
||||
).unwrap();
|
||||
if let &ConfigTypeSpecific::Type0(cfg_type0) = &device.type_specific {
|
||||
let accessor = ConfigAccessor::new(device.bus, device.device, device.function);
|
||||
for (i, &bar) in cfg_type0.bars.iter().enumerate() {
|
||||
if bar == 0x0 {
|
||||
if let Some(hdr) = EndpointHeader::from_header(common_hdr, PortAccessor) {
|
||||
let mut i = 0;
|
||||
while i < MAX_BARS as u8 {
|
||||
let Some(bar) = hdr.bar(i, PortAccessor) else {
|
||||
i += 1;
|
||||
continue;
|
||||
}
|
||||
let bar_idx = (i + 0x4) as u8;
|
||||
accessor.write(bar_idx, 0xFFFF_FFFF);
|
||||
let bar_tmp = accessor.read(bar_idx);
|
||||
let info_bits = if bar & 0x1 == 1 {
|
||||
bar_tmp & !0x3
|
||||
} else {
|
||||
bar_tmp & !0xF
|
||||
};
|
||||
let size = !(info_bits) + 1;
|
||||
accessor.write(bar_idx, bar);
|
||||
if bar & 0x1 == 1 {
|
||||
syslog_client.send_text_message("pci", format!("BAR {}: IO {:#x}, size {:#x}", i, bar & (!0x3), size)).unwrap();
|
||||
} else {
|
||||
syslog_client.send_text_message("pci", format!("BAR {}: MEM {:#x}, size {:#x}", i, bar & (!0xF), size)).unwrap();
|
||||
match bar {
|
||||
Bar::Memory32 {
|
||||
address,
|
||||
size,
|
||||
prefetchable: _,
|
||||
} => {
|
||||
syslog_client
|
||||
.send_text_message(
|
||||
"pci",
|
||||
format!("BAR {i}: MEM 32 {address:#x}, size {size:#x}"),
|
||||
)
|
||||
.unwrap();
|
||||
}
|
||||
Bar::Memory64 {
|
||||
address,
|
||||
size,
|
||||
prefetchable: _,
|
||||
} => {
|
||||
syslog_client
|
||||
.send_text_message(
|
||||
"pci",
|
||||
format!("BAR {i}: MEM 64 {address:#x}, size {size:#x}"),
|
||||
)
|
||||
.unwrap();
|
||||
i += 1;
|
||||
}
|
||||
Bar::Io { port } => {
|
||||
syslog_client
|
||||
.send_text_message("pci", format!("BAR {i}: IO {port:#x}"))
|
||||
.unwrap();
|
||||
}
|
||||
}
|
||||
i += 1;
|
||||
}
|
||||
if hdr.status(PortAccessor).has_capability_list() {
|
||||
syslog_client
|
||||
.send_text_message("pci", "Capabilities supported")
|
||||
.unwrap();
|
||||
for capability in hdr.capabilities(PortAccessor) {
|
||||
match capability {
|
||||
PciCapability::PowerManagement(_) => syslog_client
|
||||
.send_text_message("pci", "Power management capability")
|
||||
.unwrap(),
|
||||
PciCapability::AcceleratedGraphicsPort(_) => syslog_client
|
||||
.send_text_message("pci", "AGP capability")
|
||||
.unwrap(),
|
||||
PciCapability::VitalProductData(_) => syslog_client
|
||||
.send_text_message("pci", "Vital product data capability")
|
||||
.unwrap(),
|
||||
PciCapability::SlotIdentification(_) => syslog_client
|
||||
.send_text_message("pci", "External expansion capability")
|
||||
.unwrap(),
|
||||
PciCapability::Msi(_) => syslog_client
|
||||
.send_text_message("pci", "MSI capability")
|
||||
.unwrap(),
|
||||
PciCapability::CompactPCIHotswap(_) => syslog_client
|
||||
.send_text_message("pci", "CompactPCI Hotswap capability")
|
||||
.unwrap(),
|
||||
PciCapability::PciX(_) => syslog_client
|
||||
.send_text_message("pci", "PCI-X capability")
|
||||
.unwrap(),
|
||||
PciCapability::HyperTransport(_) => syslog_client
|
||||
.send_text_message("pci", "HyperTransport capability")
|
||||
.unwrap(),
|
||||
PciCapability::Vendor(_) => syslog_client
|
||||
.send_text_message("pci", "Vendor specific capability")
|
||||
.unwrap(),
|
||||
PciCapability::DebugPort(_) => syslog_client
|
||||
.send_text_message("pci", "Debug port capability")
|
||||
.unwrap(),
|
||||
PciCapability::CompactPCICentralResourceControl(_) => syslog_client
|
||||
.send_text_message("pci", "CompactPCI central resource control capability")
|
||||
.unwrap(),
|
||||
PciCapability::PciHotPlugControl(_) => syslog_client
|
||||
.send_text_message("pci", "Hotplug capability")
|
||||
.unwrap(),
|
||||
PciCapability::BridgeSubsystemVendorId(_) => syslog_client
|
||||
.send_text_message("pci", "Bridge Subsystem Vendor ID capability")
|
||||
.unwrap(),
|
||||
PciCapability::AGP3(_) => syslog_client
|
||||
.send_text_message("pci", "AGP3 capability")
|
||||
.unwrap(),
|
||||
PciCapability::PciExpress(_) => syslog_client
|
||||
.send_text_message("pci", "PCI-Express capability")
|
||||
.unwrap(),
|
||||
PciCapability::MsiX(_) => syslog_client
|
||||
.send_text_message("pci", "MSI-X capability")
|
||||
.unwrap(),
|
||||
PciCapability::Unknown { address: _, id } => syslog_client
|
||||
.send_text_message("pci", format!("Other capability (type {id:#x})")).unwrap(),
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
//if cfg_type0.status & 0x10 > 0 {
|
||||
// syslog_client
|
||||
// .send_text_message("pci", "Capabilities supported")
|
||||
// .unwrap();
|
||||
// let mut cap_ptr = cfg_type0.cap_ptr & 0xFC;
|
||||
// while cap_ptr > 0 {
|
||||
// let cap_reg0 = accessor.read(cap_ptr / 4);
|
||||
// let typ = (cap_reg0 & 0xFF) as u8;
|
||||
// if typ == 0x9 && device.common.vendor_id == 0x1AF4 {
|
||||
// let cfg_typ = ((cap_reg0 >> 24) & 0xFF) as u8;
|
||||
// let bar = accessor.read((cap_ptr / 4) + 1) as u8;
|
||||
// let offfset = accessor.read((cap_ptr / 4) + 2);
|
||||
// let length = accessor.read((cap_ptr / 4) + 3);
|
||||
// syslog_client.send_text_message("pci", format!("Virtio capability type {}, BAR {}, offfset {:#x}, length {:#x} found", cfg_typ, bar, offfset, length)).unwrap();
|
||||
// } else if typ == 0x5 {
|
||||
// let control = ((cap_reg0 >> 16) & 0xFFFF) as u16;
|
||||
// let en = (control & 0x1) > 0;
|
||||
// let mmc = (control & 0xE) as u8;
|
||||
// let mme = ((control & 0x70) >> 4) as u8;
|
||||
// let address = if (control & 0x80) > 0 {
|
||||
// let address_low = accessor.read((cap_ptr / 4) + 1);
|
||||
// let address_high = accessor.read((cap_ptr / 4) + 2);
|
||||
// ((address_high as u64) << 32) | (address_low as u64)
|
||||
// } else {
|
||||
// let address = accessor.read((cap_ptr / 4) + 1);
|
||||
// address as u64
|
||||
// };
|
||||
// let data = if (control & 0x80) > 0 {
|
||||
// accessor.read((cap_ptr / 4) + 3) as u16
|
||||
// } else {
|
||||
// accessor.read((cap_ptr / 4) + 2) as u16
|
||||
// };
|
||||
// if (control & 0x100) > 0 {
|
||||
// let mask = accessor.read((cap_ptr / 4) + 4);
|
||||
// syslog_client.send_text_message("pci", format!("MSI capability: en = {en:?}, mmc = {mmc}, mme = {mme}, addr = {address:#x}, data = {data:#x}, mask = {mask:#x}")).unwrap();
|
||||
// } else {
|
||||
// syslog_client.send_text_message("pci", format!("MSI capability: en = {en:?}, mmc = {mmc}, mme = {mme}, addr = {address:#x}, data = {data:#x}, no masking")).unwrap();
|
||||
// }
|
||||
// } else if typ == 0x11 {
|
||||
// let control = ((cap_reg0 >> 16) & 0xFFFF) as u16;
|
||||
// let en = (control & 0x8000) > 0;
|
||||
// let mask_all = (control & 0x4000) > 0;
|
||||
// let size = (control & 0x7FF) + 1;
|
||||
// let cap_reg1 = accessor.read((cap_ptr / 4) + 1);
|
||||
// let table_bar = (cap_reg1 & 0x7) as u8;
|
||||
// let table_offset = cap_reg1 & 0xFFFF_FFF8;
|
||||
// let cap_reg2 = accessor.read((cap_ptr / 4) + 1);
|
||||
// let pending_bar = (cap_reg2 & 0x7) as u8;
|
||||
// let pending_offset = cap_reg2 & 0xFFFF_FFF8;
|
||||
// syslog_client.send_text_message("pci", format!("MSI-X capability: en = {en:?}, mask_all = {mask_all:?}, size = {size}, table_bar = {table_bar}, table_offset = {table_offset:#x}, pending_bar = {pending_bar}, pending_offset = {pending_offset:#x}")).unwrap();
|
||||
// } else {
|
||||
// syslog_client
|
||||
// .send_text_message("pci", format!("Capability {:#x} found", typ))
|
||||
// .unwrap();
|
||||
// }
|
||||
// cap_ptr = ((cap_reg0 >> 8) & 0xFF) as u8;
|
||||
// }
|
||||
// }
|
||||
//}
|
||||
let driver = config
|
||||
.mappings
|
||||
.iter()
|
||||
.find(|mapping| match mapping {
|
||||
DriverMapping::GenericClass {
|
||||
class,
|
||||
class: drv_class,
|
||||
vend_dev_exclude,
|
||||
..
|
||||
} => {
|
||||
&device.class == class
|
||||
&& !vend_dev_exclude.as_ref().map_or(false, |x| {
|
||||
x.contains(&(device.common.vendor_id, device.common.device_id))
|
||||
})
|
||||
}
|
||||
DriverMapping::VendDev { list, .. } => {
|
||||
list.contains(&(device.common.vendor_id, device.common.device_id))
|
||||
&class == drv_class
|
||||
&& !vend_dev_exclude
|
||||
.as_ref()
|
||||
.map_or(false, |x| x.contains(&(vid, pid)))
|
||||
}
|
||||
DriverMapping::VendDev { list, .. } => list.contains(&(vid, pid)),
|
||||
})
|
||||
.map(|mapping| mapping.path());
|
||||
if let Some(driver) = driver {
|
||||
@ -421,7 +373,11 @@ fn main() {
|
||||
.send_text_message("pci", format!(" Driver {}", driver.display()))
|
||||
.unwrap();
|
||||
|
||||
driver_map.entry(driver.to_owned()).or_default().push((device.bus, device.device, device.function));
|
||||
driver_map.entry(driver.to_owned()).or_default().push((
|
||||
address.bus(),
|
||||
address.device(),
|
||||
address.function(),
|
||||
));
|
||||
} else {
|
||||
syslog_client
|
||||
.send_text_message("pci", " WARN: No driver")
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user