From a5b6b26b5eff24df179ef0a4528cb60970b702c8 Mon Sep 17 00:00:00 2001 From: pjht Date: Sun, 25 Sep 2022 16:00:30 -0500 Subject: [PATCH] Initial commit --- .gitignore | 31 + memory_pgm.kicad_sch | 3157 ++++++++++++++++++++++++++++++++++++++++++ ram_rom-cache.lib | 61 + ram_rom-rescue.dcm | 3 + ram_rom-rescue.lib | 80 ++ ram_rom.kicad_pcb | 342 +++++ ram_rom.kicad_pro | 423 ++++++ ram_rom.kicad_sch | 1351 ++++++++++++++++++ ram_rom.sch | 27 + sym-lib-table | 4 + 10 files changed, 5479 insertions(+) create mode 100644 .gitignore create mode 100644 memory_pgm.kicad_sch create mode 100644 ram_rom-cache.lib create mode 100644 ram_rom-rescue.dcm create mode 100644 ram_rom-rescue.lib create mode 100644 ram_rom.kicad_pcb create mode 100644 ram_rom.kicad_pro create mode 100644 ram_rom.kicad_sch create mode 100644 ram_rom.sch create mode 100644 sym-lib-table diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..460fe60 --- /dev/null +++ b/.gitignore @@ -0,0 +1,31 @@ +# For PCBs designed using KiCad: https://www.kicad.org/ +# Format documentation: https://kicad.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*.kicad_sch-bak +*-backups +*.kicad_prl +*.sch-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache +\#autosaved_files# + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv +Footer diff --git a/memory_pgm.kicad_sch b/memory_pgm.kicad_sch new file mode 100644 index 0000000..3f94e82 --- /dev/null +++ b/memory_pgm.kicad_sch @@ -0,0 +1,3157 @@ +(kicad_sch (version 20211123) (generator eeschema) + + (uuid 8926acd8-fb2e-4446-b245-bd474fa2d387) + + (paper "A4") + + (lib_symbols + (symbol "74xx:74HC245" (pin_names (offset 1.016)) (in_bom yes) (on_board yes) + (property "Reference" "U" (id 0) (at -7.62 16.51 0) + (effects (font (size 1.27 1.27))) + ) + (property "Value" "74HC245" (id 1) (at -7.62 -16.51 0) + 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(id 0) (at 202.6794 82.6602 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Value" "CY62256-70PC" (id 1) (at 202.6794 85.1971 0) + (effects (font (size 1.27 1.27)) (justify left)) + ) + (property "Footprint" "Package_DIP:DIP-28_W15.24mm" (id 2) (at 200.66 109.22 0) + (effects (font (size 1.27 1.27)) hide) + ) + (property "Datasheet" "https://ecee.colorado.edu/~mcclurel/Cypress_SRAM_CY62256.pdf" (id 3) (at 200.66 109.22 0) + (effects (font (size 1.27 1.27)) hide) + ) + (pin "14" (uuid 999c95bf-fed5-4ccb-bef2-b3832451769e)) + (pin "28" (uuid f3d52c4f-1a10-4edd-81ad-65d7ed8bf26a)) + (pin "1" (uuid 7bdeef48-b5eb-49c2-8142-7c295708cca4)) + (pin "10" (uuid 4d2272f0-f20f-4e54-98a0-df55636d5cf6)) + (pin "11" (uuid 80b46705-fd2f-4f0d-af34-90ca86fbfa0c)) + (pin "12" (uuid 0c0137df-21cc-4b5d-a46b-cd1094cf5c53)) + (pin "13" (uuid a14768b4-2cb1-4406-b0f6-996f09f43ff0)) + (pin "15" (uuid 7ea35161-d236-41d4-bc87-bfa479005c2e)) + (pin "16" (uuid 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cde4f3bc-b333-4551-9d85-f52407bff6c8)) + (pin "8" (uuid 242170e7-0859-4950-9edc-321feab28e77)) + (pin "9" (uuid 759dba31-781d-4c7a-b749-b0f441c1575d)) + ) +) diff --git a/ram_rom-cache.lib b/ram_rom-cache.lib new file mode 100644 index 0000000..bcf0b51 --- /dev/null +++ b/ram_rom-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# symbols_Bus_Peripheral +# +DEF symbols_Bus_Peripheral J 0 40 Y Y 1 F N +F0 "J" -100 2350 50 H V C CNN +F1 "symbols_Bus_Peripheral" -100 2300 50 H V C CNN +F2 "Connector_PCBEdge:BUS_PCIexpress_x4" 100 2400 50 H I C CNN +F3 "" 100 2400 50 H I C CNN +DRAW +S 100 2250 -300 -2250 0 1 0 f +X 5V A1 300 2200 200 L 50 50 1 1 W +X A7 A10 300 1300 200 L 50 50 1 1 B +X A8 A11 300 1200 200 L 50 50 1 1 B +X A9 A12 300 1100 200 L 50 50 1 1 B +X A10 A13 300 1000 200 L 50 50 1 1 B +X A11 A14 300 900 200 L 50 50 1 1 B +X A12 A15 300 800 200 L 50 50 1 1 B +X A13 A16 300 700 200 L 50 50 1 1 B +X A14 A17 300 600 200 L 50 50 1 1 B +X A15 A18 300 500 200 L 50 50 1 1 B +X D0 A19 300 400 200 L 50 50 1 1 B +X GND A2 300 2100 200 L 50 50 1 1 W +X D1 A20 300 300 200 L 50 50 1 1 B +X D2 A21 300 200 200 L 50 50 1 1 B +X D3 A22 300 100 200 L 50 50 1 1 B +X D4 A23 300 0 200 L 50 50 1 1 B +X D5 A24 300 -100 200 L 50 50 1 1 B +X D6 A25 300 -200 200 L 50 50 1 1 B +X D7 A26 300 -300 200 L 50 50 1 1 B +X ~IORQ A27 300 -400 200 L 50 50 1 1 B +X ~MREQ A28 300 -500 200 L 50 50 1 1 B +X ~WR A29 300 -600 200 L 50 50 1 1 B +X A0 A3 300 2000 200 L 50 50 1 1 B +X ~RD A30 300 -700 200 L 50 50 1 1 B +X ~HALT A31 300 -800 200 L 50 50 1 1 I +X ~WAIT A32 300 -900 200 L 50 50 1 1 C +X A1 A4 300 1900 200 L 50 50 1 1 B +X A2 A5 300 1800 200 L 50 50 1 1 B +X A3 A6 300 1700 200 L 50 50 1 1 B +X A4 A7 300 1600 200 L 50 50 1 1 B +X A5 A8 300 1500 200 L 50 50 1 1 B +X A6 A9 300 1400 200 L 50 50 1 1 B +X ~RFSH B1 300 -1000 200 L 50 50 1 1 I +X IEI B10 300 -1900 200 L 50 50 1 1 I +X BEO B11 300 -2000 200 L 50 50 1 1 O +X BEI B12 300 -2100 200 L 50 50 1 1 I +X ~ACCESS B13 300 -2200 200 L 50 50 1 1 I +X ~M1 B2 300 -1100 200 L 50 50 1 1 I +X ~INT B3 300 -1200 200 L 50 50 1 1 C +X ~NMI B4 300 -1300 200 L 50 50 1 1 C +X ~BUSACK B5 300 -1400 200 L 50 50 1 1 I +X ~BUSRQ B6 300 -1500 200 L 50 50 1 1 O +X CLK B7 300 -1600 200 L 50 50 1 1 I +X ~RESET B8 300 -1700 200 L 50 50 1 1 B +X IEO B9 300 -1800 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/ram_rom-rescue.dcm b/ram_rom-rescue.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/ram_rom-rescue.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/ram_rom-rescue.lib b/ram_rom-rescue.lib new file mode 100644 index 0000000..d80830b --- /dev/null +++ b/ram_rom-rescue.lib @@ -0,0 +1,80 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# C64AB-symbols +# +DEF C64AB-symbols J 0 20 Y Y 1 F N +F0 "J" 0 3350 50 H V C CNN +F1 "C64AB-symbols" 250 50 50 V V C CNN +F2 "" 0 50 50 H I C CNN +F3 "" 0 50 50 H I C CNN +DRAW +S -150 -3200 150 3300 0 1 10 f +X 1A a1 -300 3200 150 R 50 50 1 1 P +X 10A a10 -300 1400 150 R 50 50 1 1 P +X 11A a11 -300 1200 150 R 50 50 1 1 P +X 12A a12 -300 1000 150 R 50 50 1 1 P +X 13A a13 -300 800 150 R 50 50 1 1 P +X 14A a14 -300 600 150 R 50 50 1 1 P +X 15A a15 -300 400 150 R 50 50 1 1 P +X 16A a16 -300 200 150 R 50 50 1 1 P +X 17A a17 -300 0 150 R 50 50 1 1 P +X 18A a18 -300 -200 150 R 50 50 1 1 P +X 19A a19 -300 -400 150 R 50 50 1 1 P +X 2A a2 -300 3000 150 R 50 50 1 1 P +X 20A a20 -300 -600 150 R 50 50 1 1 P +X 21A a21 -300 -800 150 R 50 50 1 1 P +X 22A a22 -300 -1000 150 R 50 50 1 1 P +X 23A a23 -300 -1200 150 R 50 50 1 1 P +X 24A a24 -300 -1400 150 R 50 50 1 1 P +X 25A a25 -300 -1600 150 R 50 50 1 1 P +X 26A a26 -300 -1800 150 R 50 50 1 1 P +X 27A a27 -300 -2000 150 R 50 50 1 1 P +X 28A a28 -300 -2200 150 R 50 50 1 1 P +X 29A a29 -300 -2400 150 R 50 50 1 1 P +X 3A a3 -300 2800 150 R 50 50 1 1 P +X 30A a30 -300 -2600 150 R 50 50 1 1 P +X 31A a31 -300 -2800 150 R 50 50 1 1 P +X 32A a32 -300 -3000 150 R 50 50 1 1 P +X 4A a4 -300 2600 150 R 50 50 1 1 P +X 5A a5 -300 2400 150 R 50 50 1 1 P +X 6A a6 -300 2200 150 R 50 50 1 1 P +X 7A a7 -300 2000 150 R 50 50 1 1 P +X 8A a8 -300 1800 150 R 50 50 1 1 P +X 9A a9 -300 1600 150 R 50 50 1 1 P +X 1B b1 -300 3100 150 R 50 50 1 1 P +X 10B b10 -300 1300 150 R 50 50 1 1 P +X 11B b11 -300 1100 150 R 50 50 1 1 P +X 12B b12 -300 900 150 R 50 50 1 1 P +X 13B b13 -300 700 150 R 50 50 1 1 P +X 14B b14 -300 500 150 R 50 50 1 1 P +X 15B b15 -300 300 150 R 50 50 1 1 P +X 16B b16 -300 100 150 R 50 50 1 1 P +X 17B b17 -300 -100 150 R 50 50 1 1 P +X 18B b18 -300 -300 150 R 50 50 1 1 P +X 19B b19 -300 -500 150 R 50 50 1 1 P +X 2B b2 -300 2900 150 R 50 50 1 1 P +X 20B b20 -300 -700 150 R 50 50 1 1 P +X 21B b21 -300 -900 150 R 50 50 1 1 P +X 22B b22 -300 -1100 150 R 50 50 1 1 P +X 23B b23 -300 -1300 150 R 50 50 1 1 P +X 24B b24 -300 -1500 150 R 50 50 1 1 P +X 25B b25 -300 -1700 150 R 50 50 1 1 P +X 26B b26 -300 -1900 150 R 50 50 1 1 P +X 27B b27 -300 -2100 150 R 50 50 1 1 P +X 28B b28 -300 -2300 150 R 50 50 1 1 P +X 29B b29 -300 -2500 150 R 50 50 1 1 P +X 3B b3 -300 2700 150 R 50 50 1 1 P +X 30B b30 -300 -2700 150 R 50 50 1 1 P +X 31B b31 -300 -2900 150 R 50 50 1 1 P +X 32B b32 -300 -3100 150 R 50 50 1 1 P +X 4B b4 -300 2500 150 R 50 50 1 1 P +X 5B b5 -300 2300 150 R 50 50 1 1 P +X 6B b6 -300 2100 150 R 50 50 1 1 P +X 7B b7 -300 1900 150 R 50 50 1 1 P +X 8B b8 -300 1700 150 R 50 50 1 1 P +X 9B b9 -300 1500 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/ram_rom.kicad_pcb b/ram_rom.kicad_pcb new file mode 100644 index 0000000..16dfe9d --- /dev/null +++ b/ram_rom.kicad_pcb @@ -0,0 +1,342 @@ +(kicad_pcb (version 20171130) (host pcbnew 5.1.10) + + (general + (thickness 1.6) + (drawings 4) + (tracks 0) + (zones 0) + (modules 1) + (nets 46) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (edge_width 0.05) + (segment_width 0.2) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.12) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes true) + (usegerberadvancedattributes true) + (creategerberjobfile true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 "Net-(J1-PadA32)") + (net 2 "Net-(J1-PadA31)") + (net 3 "Net-(J1-PadA30)") + (net 4 "Net-(J1-PadA29)") + (net 5 "Net-(J1-PadA28)") + (net 6 "Net-(J1-PadA27)") + (net 7 "Net-(J1-PadA26)") + (net 8 "Net-(J1-PadA25)") + (net 9 "Net-(J1-PadA24)") + (net 10 "Net-(J1-PadA23)") + (net 11 "Net-(J1-PadA22)") + (net 12 "Net-(J1-PadA21)") + (net 13 "Net-(J1-PadA20)") + (net 14 "Net-(J1-PadA19)") + (net 15 "Net-(J1-PadB1)") + (net 16 "Net-(J1-PadB2)") + (net 17 "Net-(J1-PadB3)") + (net 18 "Net-(J1-PadB4)") + (net 19 "Net-(J1-PadB5)") + (net 20 "Net-(J1-PadB6)") + (net 21 "Net-(J1-PadB7)") + (net 22 "Net-(J1-PadB8)") + (net 23 "Net-(J1-PadB9)") + (net 24 "Net-(J1-PadB10)") + (net 25 "Net-(J1-PadB11)") + (net 26 "Net-(J1-PadB12)") + (net 27 "Net-(J1-PadB13)") + (net 28 "Net-(J1-PadA1)") + (net 29 "Net-(J1-PadA2)") + (net 30 "Net-(J1-PadA3)") + (net 31 "Net-(J1-PadA4)") + (net 32 "Net-(J1-PadA5)") + (net 33 "Net-(J1-PadA6)") + (net 34 "Net-(J1-PadA7)") + (net 35 "Net-(J1-PadA8)") + (net 36 "Net-(J1-PadA9)") + (net 37 "Net-(J1-PadA10)") + (net 38 "Net-(J1-PadA11)") + (net 39 "Net-(J1-PadA14)") + (net 40 "Net-(J1-PadA15)") + (net 41 "Net-(J1-PadA16)") + (net 42 "Net-(J1-PadA17)") + (net 43 "Net-(J1-PadA18)") + (net 44 "Net-(J1-PadA12)") + (net 45 "Net-(J1-PadA13)") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net "Net-(J1-PadA1)") + (add_net "Net-(J1-PadA10)") + (add_net "Net-(J1-PadA11)") + (add_net "Net-(J1-PadA12)") + (add_net "Net-(J1-PadA13)") + (add_net "Net-(J1-PadA14)") + (add_net "Net-(J1-PadA15)") + (add_net "Net-(J1-PadA16)") + (add_net "Net-(J1-PadA17)") + (add_net "Net-(J1-PadA18)") + (add_net "Net-(J1-PadA19)") + (add_net "Net-(J1-PadA2)") + (add_net "Net-(J1-PadA20)") + (add_net "Net-(J1-PadA21)") + (add_net "Net-(J1-PadA22)") + (add_net "Net-(J1-PadA23)") + (add_net "Net-(J1-PadA24)") + (add_net "Net-(J1-PadA25)") + (add_net "Net-(J1-PadA26)") + (add_net "Net-(J1-PadA27)") + (add_net "Net-(J1-PadA28)") + (add_net "Net-(J1-PadA29)") + (add_net "Net-(J1-PadA3)") + (add_net "Net-(J1-PadA30)") + (add_net "Net-(J1-PadA31)") + (add_net "Net-(J1-PadA32)") + (add_net "Net-(J1-PadA4)") + (add_net "Net-(J1-PadA5)") + (add_net "Net-(J1-PadA6)") + (add_net "Net-(J1-PadA7)") + (add_net "Net-(J1-PadA8)") + (add_net "Net-(J1-PadA9)") + (add_net "Net-(J1-PadB1)") + (add_net "Net-(J1-PadB10)") + (add_net "Net-(J1-PadB11)") + (add_net "Net-(J1-PadB12)") + (add_net "Net-(J1-PadB13)") + (add_net "Net-(J1-PadB2)") + (add_net "Net-(J1-PadB3)") + (add_net "Net-(J1-PadB4)") + (add_net "Net-(J1-PadB5)") + (add_net "Net-(J1-PadB6)") + (add_net "Net-(J1-PadB7)") + (add_net "Net-(J1-PadB8)") + (add_net "Net-(J1-PadB9)") + ) + + (module Connector_PCBEdge:BUS_PCIexpress_x4 (layer F.Cu) (tedit 5DBD33F7) (tstamp 614245A5) + (at 50.67 131.58) + (descr "PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70") + (tags PCIe) + (path /614249FA) + (attr virtual) + (fp_text reference J1 (at 5 -3.5) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Bus_Peripheral (at 10.33 -8.01) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user %R (at 16 -3.5) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user "PCB Thickness 1.57 mm" (at 5 2.8 180) (layer Cmts.User) + (effects (font (size 0.5 0.5) (thickness 0.1))) + ) + (fp_arc (start 11.5 -4) (end 12.45 -4) (angle -180) (layer Edge.Cuts) (width 0.1)) + (fp_line (start 33.65 2.95) (end 33.15 3.45) (layer Edge.Cuts) (width 0.1)) + (fp_line (start 12.45 2.95) (end 12.95 3.45) (layer Edge.Cuts) (width 0.1)) + (fp_line (start 10.55 2.95) (end 10.05 3.45) (layer Edge.Cuts) (width 0.1)) + (fp_line (start -0.65 2.95) (end -0.15 3.45) (layer Edge.Cuts) (width 0.1)) + (fp_line (start 12.95 3.45) (end 33.15 3.45) (layer Edge.Cuts) (width 0.1)) + (fp_line (start 33.65 -4.95) (end 33.65 2.95) (layer Edge.Cuts) (width 0.1)) + (fp_line (start -0.15 3.45) (end 10.05 3.45) (layer Edge.Cuts) (width 0.1)) + (fp_line (start -0.65 -4.95) (end -0.65 2.95) (layer Edge.Cuts) (width 0.1)) + (fp_line (start 12.45 -4) (end 12.45 2.95) (layer Edge.Cuts) (width 0.1)) + (fp_line (start 10.55 -4) (end 10.55 2.95) (layer Edge.Cuts) (width 0.1)) + (fp_line (start 34.15 3.95) (end -1.15 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start 34.15 3.95) (end 34.15 -5.45) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.15 -5.45) (end -1.15 3.95) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.15 -5.45) (end 34.15 -5.45) (layer F.CrtYd) (width 0.05)) + (pad A32 connect rect (at 33 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 1 "Net-(J1-PadA32)")) + (pad A31 connect rect (at 32 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 2 "Net-(J1-PadA31)")) + (pad A30 connect rect (at 31 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 3 "Net-(J1-PadA30)")) + (pad A29 connect rect (at 30 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 4 "Net-(J1-PadA29)")) + (pad A28 connect rect (at 29 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 5 "Net-(J1-PadA28)")) + (pad A27 connect rect (at 28 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 6 "Net-(J1-PadA27)")) + (pad A26 connect rect (at 27 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 7 "Net-(J1-PadA26)")) + (pad A25 connect rect (at 26 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 8 "Net-(J1-PadA25)")) + (pad A24 connect rect (at 25 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 9 "Net-(J1-PadA24)")) + (pad A23 connect rect (at 24 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 10 "Net-(J1-PadA23)")) + (pad A22 connect rect (at 23 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 11 "Net-(J1-PadA22)")) + (pad A21 connect rect (at 22 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 12 "Net-(J1-PadA21)")) + (pad A20 connect rect (at 21 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 13 "Net-(J1-PadA20)")) + (pad A19 connect rect (at 20 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 14 "Net-(J1-PadA19)")) + (pad B32 connect rect (at 33 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B31 connect rect (at 32 -0.55) (size 0.7 3.2) (layers F.Cu F.Mask)) + (pad B30 connect rect (at 31 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B29 connect rect (at 30 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B28 connect rect (at 29 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B27 connect rect (at 28 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B26 connect rect (at 27 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B25 connect rect (at 26 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B24 connect rect (at 25 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B23 connect rect (at 24 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B22 connect rect (at 23 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B21 connect rect (at 22 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B20 connect rect (at 21 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B19 connect rect (at 20 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B1 connect rect (at 0 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 15 "Net-(J1-PadB1)")) + (pad B2 connect rect (at 1 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 16 "Net-(J1-PadB2)")) + (pad B3 connect rect (at 2 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 17 "Net-(J1-PadB3)")) + (pad B4 connect rect (at 3 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 18 "Net-(J1-PadB4)")) + (pad B5 connect rect (at 4 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 19 "Net-(J1-PadB5)")) + (pad B6 connect rect (at 5 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 20 "Net-(J1-PadB6)")) + (pad B7 connect rect (at 6 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 21 "Net-(J1-PadB7)")) + (pad B8 connect rect (at 7 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 22 "Net-(J1-PadB8)")) + (pad B9 connect rect (at 8 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 23 "Net-(J1-PadB9)")) + (pad B10 connect rect (at 9 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 24 "Net-(J1-PadB10)")) + (pad B11 connect rect (at 10 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 25 "Net-(J1-PadB11)")) + (pad B14 connect rect (at 15 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B15 connect rect (at 16 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B16 connect rect (at 17 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B17 connect rect (at 18 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B18 connect rect (at 19 0) (size 0.7 4.3) (layers F.Cu F.Mask)) + (pad B12 connect rect (at 13 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 26 "Net-(J1-PadB12)")) + (pad B13 connect rect (at 14 0) (size 0.7 4.3) (layers F.Cu F.Mask) + (net 27 "Net-(J1-PadB13)")) + (pad A1 connect rect (at 0 -0.55) (size 0.7 3.2) (layers B.Cu B.Mask) + (net 28 "Net-(J1-PadA1)")) + (pad A2 connect rect (at 1 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 29 "Net-(J1-PadA2)")) + (pad A3 connect rect (at 2 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 30 "Net-(J1-PadA3)")) + (pad A4 connect rect (at 3 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 31 "Net-(J1-PadA4)")) + (pad A5 connect rect (at 4 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 32 "Net-(J1-PadA5)")) + (pad A6 connect rect (at 5 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 33 "Net-(J1-PadA6)")) + (pad A7 connect rect (at 6 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 34 "Net-(J1-PadA7)")) + (pad A8 connect rect (at 7 0) (size 0.7 4.3) (layers B.Cu B.Mask) + (net 35 "Net-(J1-PadA8)")) + (pad A9 connect rect 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