m68k-backplane-computer/emu
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Revert changing the MMU TLB to be accessible via memory

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This commit is contained in:
pjht 2023-11-02 18:41:01 -05:00
parent e840a301b3
commit cb12ab55c2
Signed by: pjht
GPG Key ID: 7B5F6AFBEC7EE78E
1 changed files with 26 additions and 62 deletions
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88
src/mmu.rs
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@ -23,9 +23,7 @@ pub struct MmuCard {
map_frames: [u32; 4], map_frames: [u32; 4],
map_frames_enabled: [bool; 4], map_frames_enabled: [bool; 4],
print_debug: bool, print_debug: bool,
tlb_high_write_word: u16, tlb_clear_entry: u16,
tlb_mem_start: u32,
tlb_mem_enabled: bool,
} }
impl Card for MmuCard { impl Card for MmuCard {
@ -36,9 +34,7 @@ impl Card for MmuCard {
map_frames: [0; 4], map_frames: [0; 4],
map_frames_enabled: [false; 4], map_frames_enabled: [false; 4],
print_debug: false, print_debug: false,
tlb_high_write_word: 0, tlb_clear_entry: 0,
tlb_mem_start: 0,
tlb_mem_enabled: false,
}) })
} }
@ -46,38 +42,6 @@ impl Card for MmuCard {
Some(self) Some(self)
} }
fn read_byte(&mut self, address: u32) -> NullableResult<u8, BusError> {
if !self.tlb_mem_enabled || address >> 15 != self.tlb_mem_start {
return NullableResult::Null;
}
let address = address & 0x7FFF;
NullableResult::Ok(u32_get_be_byte(
self.tlb[(address as usize) >> 2],
address as u8 & 0x2,
))
}
fn write_byte(&mut self, address: u32, _data: u8) -> NullableResult<(), BusError> {
if !self.tlb_mem_enabled || address >> 15 != self.tlb_mem_start {
return NullableResult::Null;
}
NullableResult::Err(BusError)
}
fn write_word(&mut self, address: u32, data: u16) -> NullableResult<(), BusError> {
if !self.tlb_mem_enabled || address >> 15 != self.tlb_mem_start {
return NullableResult::Null;
}
if address & 0x1 == 0 {
self.tlb_high_write_word = data;
NullableResult::Ok(())
} else {
self.tlb[(address >> 1) as usize] =
((self.tlb_high_write_word as u32) << 16) | (data as u32);
NullableResult::Ok(())
}
}
fn read_byte_io(&mut self, address: u8) -> NullableResult<u8, BusError> { fn read_byte_io(&mut self, address: u8) -> NullableResult<u8, BusError> {
match address { match address {
(0x0..=0xF) => { (0x0..=0xF) => {
@ -117,30 +81,30 @@ impl Card for MmuCard {
_ => unreachable!(), _ => unreachable!(),
}; };
} }
// (0x10..=0x13) => { (0x10..=0x13) => {
// let offset = (address - 0x10) % 4; let offset = (address - 0x10) % 4;
// match offset { match offset {
// 0 => (), 0 => (),
// 1 => { 1 => {
// self.tlb_clear_entry = (self.tlb_clear_entry & 0xF) | ((data as u16) << 4); self.tlb_clear_entry = (self.tlb_clear_entry & 0xF) | ((data as u16) << 4);
// } }
// 2 => { 2 => {
// self.tlb_clear_entry = self.tlb_clear_entry =
// (self.tlb_clear_entry & 0xFF0) | (((data as u16) & 0xF0) >> 4); (self.tlb_clear_entry & 0xFF0) | (((data as u16) & 0xF0) >> 4);
// } }
// 3 => { 3 => {
// if self.print_debug { if self.print_debug {
// println!( println!(
// "Clearing TLB entry {:#x} ( page start {:#x} )", "Clearing TLB entry {:#x} ( page start {:#x} )",
// self.tlb_clear_entry, self.tlb_clear_entry,
// (self.tlb_clear_entry as u32) << 12 (self.tlb_clear_entry as u32) << 12
// ); );
// } }
// self.tlb[self.tlb_clear_entry as usize] = 0x0; self.tlb[self.tlb_clear_entry as usize] = 0x0;
// } }
// _ => unreachable!(), _ => unreachable!(),
// } }
// } }
0x15 => { 0x15 => {
self.enabled = (data & 0x1) > 0; self.enabled = (data & 0x1) > 0;
} }