m68k-backplane-computer/emu
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Clean up code

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This commit is contained in:
pjht 2023-03-15 18:59:38 -05:00
parent d32bcc3a8e
commit a0eaccaf7f
Signed by: pjht
GPG Key ID: 7B5F6AFBEC7EE78E
7 changed files with 27 additions and 27 deletions
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2
src/disas.rs
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@ -69,7 +69,7 @@ impl<T: Display> Display for DisassemblyError<T> {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
match self {
Self::InvalidInstruction => f.write_str("Invalid instruction"),
Self::ReadError(e) => f.write_fmt(format_args!("{}", e)),
Self::ReadError(e) => f.write_fmt(format_args!("{e}")),
}
}
}

24
src/instruction.rs
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@ -62,23 +62,23 @@ impl From<RegisterEffective> for EffectiveAddress {
impl Display for EffectiveAddress {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
match self {
Self::DataReg(r) => f.write_fmt(format_args!("D{}", r)),
Self::AddressReg(r) => f.write_fmt(format_args!("A{}", r)),
Self::Address(r) => f.write_fmt(format_args!("(A{})", r)),
Self::AddressPostinc(r) => f.write_fmt(format_args!("(A{})+", r)),
Self::AddressPredec(r) => f.write_fmt(format_args!("-(A{})", r)),
Self::AddressDisplacement(r, d) => f.write_fmt(format_args!("({}, A{})", d, r)),
Self::DataReg(r) => f.write_fmt(format_args!("D{r}")),
Self::AddressReg(r) => f.write_fmt(format_args!("A{r}")),
Self::Address(r) => f.write_fmt(format_args!("(A{r})")),
Self::AddressPostinc(r) => f.write_fmt(format_args!("(A{r})+")),
Self::AddressPredec(r) => f.write_fmt(format_args!("-(A{r})")),
Self::AddressDisplacement(r, d) => f.write_fmt(format_args!("({d}, A{r})")),
Self::AddressIndex {
reg,
displacement,
idx,
..
} => f.write_fmt(format_args!("({}, A{}, {})", displacement, reg, idx)),
Self::PcDisplacement(_, d) => f.write_fmt(format_args!("(0x{:x}, PC)", d)),
Self::PcIndex(_, d, idx, _) => f.write_fmt(format_args!("({}, PC, {})", d, idx)),
Self::AbsoluteShort(a) => f.write_fmt(format_args!("(0x{:x}).W", a)),
Self::AbsoluteLong(a) => f.write_fmt(format_args!("(0x{:x}).L", a)),
Self::Immediate(i) => f.write_fmt(format_args!("#0x{:x}", i)),
} => f.write_fmt(format_args!("({displacement}, A{reg}, {idx})")),
Self::PcDisplacement(_, d) => f.write_fmt(format_args!("(0x{d:x}, PC)")),
Self::PcIndex(_, d, idx, _) => f.write_fmt(format_args!("({d}, PC, {idx})")),
Self::AbsoluteShort(a) => f.write_fmt(format_args!("(0x{a:x}).W")),
Self::AbsoluteLong(a) => f.write_fmt(format_args!("(0x{a:x}).L")),
Self::Immediate(i) => f.write_fmt(format_args!("#0x{i:x}")),
}
}
}

2
src/location.rs
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@ -38,7 +38,7 @@ impl<'a> Display for Displayer<'a> {
sym,
self.location.addr(self.symbol_tables)
)),
Location::Address(addr) => f.write_fmt(format_args!("{:#x}", addr)),
Location::Address(addr) => f.write_fmt(format_args!("{addr:#x}")),
}
}
}

14
src/m68k.rs
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@ -90,19 +90,19 @@ impl Display for M68K {
f.write_str("Mode: User\n")?;
}
for (i, val) in self.dregs[0..4].iter().enumerate() {
f.write_fmt(format_args!("D{}: 0x{:0>8x} ", i, val))?;
f.write_fmt(format_args!("D{i}: 0x{val:0>8x} "))?;
}
f.write_str("\n")?;
for (i, val) in self.dregs[4..8].iter().enumerate() {
f.write_fmt(format_args!("D{}: 0x{:0>8x} ", i + 4, val))?;
f.write_fmt(format_args!("D{}: 0x{val:0>8x} ", i + 4))?;
}
f.write_str("\n")?;
for (i, val) in self.aregs[0..4].iter().enumerate() {
f.write_fmt(format_args!("A{}: 0x{:0>8x} ", i, val))?;
f.write_fmt(format_args!("A{i}: 0x{val:0>8x} "))?;
}
f.write_str("\n")?;
for (i, val) in self.aregs[4..7].iter().enumerate() {
f.write_fmt(format_args!("A{}: 0x{:0>8x} ", i + 4, val))?;
f.write_fmt(format_args!("A{}: 0x{val:0>8x} ", i + 4))?;
}
if self.is_supervisor() {
f.write_fmt(format_args!("A7: 0x{:0>8x}\n", self.ssp))?;
@ -176,7 +176,7 @@ impl M68K {
Instruction::OriCcr(val) => {
self.sr = (self.sr & 0xFF00) | ((self.sr & 0xFF) | val as u16);
}
Instruction::OriSr(val) => self.sr |= val as u16,
Instruction::OriSr(val) => self.sr |= val,
Instruction::Ori(size, dst, val) => {
let dst_val = self.read_effective(dst, size)?;
let res = dst_val | val;
@ -194,7 +194,7 @@ impl M68K {
Instruction::AndiCcr(val) => {
self.sr = (self.sr & 0xFF00) | ((self.sr & 0xFF) & val as u16);
}
Instruction::AndiSr(val) => self.sr &= val as u16,
Instruction::AndiSr(val) => self.sr &= val,
Instruction::Andi(size, dst, val) => {
let dst_val = self.read_effective(dst, size)?;
let res = dst_val & val;
@ -218,7 +218,7 @@ impl M68K {
Instruction::EoriCcr(val) => {
self.sr = (self.sr & 0xFF00) | ((self.sr & 0xFF) ^ val as u16);
}
Instruction::EoriSr(val) => self.sr ^= val as u16,
Instruction::EoriSr(val) => self.sr ^= val,
Instruction::Eori(size, dst, val) => {
let dst_val = self.read_effective(dst, size)?;
let res = dst_val ^ val;

4
src/main.rs
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@ -84,7 +84,7 @@ fn main() -> Result<(), anyhow::Error> {
match state.cpu.step() {
Ok(()) => (),
Err(e) => {
println!("{}", e);
println!("{e}");
state.cpu.stopped = true;
}
}
@ -93,7 +93,7 @@ fn main() -> Result<(), anyhow::Error> {
let pc = state.cpu.pc();
out += &disas_fmt(&mut state.cpu, pc, &state.symbol_tables).0;
out.pop(); // Remove trailing newline
println!("{}", out);
println!("{out}");
return Ok(());
}
Repl::<_, anyhow::Error>::new(state)

4
src/peek.rs
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@ -20,9 +20,9 @@ impl Format {
Size::Word => num as u16 as i16 as i32,
Size::LongWord => num as i32,
};
format!("{}", num)
format!("{num}")
}
Self::UnsignedDecimal => format!("{}", num),
Self::UnsignedDecimal => format!("{num}"),
Self::Binary => format!("0b{:0>width$b}", num, width = size.byte_count() * 8),
}
}

4
src/rom.rs
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@ -78,7 +78,7 @@ impl Card for Rom {
(0..=0xEF) => NullableResult::Ok(self.ram[address as usize]),
(0xF0..=0xF1) => NullableResult::Ok(u16_get_be_byte(self.start, address - 0xF0)),
0xF3 => NullableResult::Ok(self.enabled as u8),
(0xFE..=0xFF) => NullableResult::Ok(u16_get_be_byte(0x1, address - 0xFE)),
(0xFE..=0xFF) => NullableResult::Ok(u16_get_be_byte(ID, address - 0xFE)),
_ => NullableResult::Null,
}
}
@ -115,7 +115,7 @@ impl Card for Rom {
self.data.clear();
file.read_to_end(&mut self.data)
.map_err(|e| anyhow!("Failed to read ROM image file {} ({})", file_name, e))?;
println!("Reloaded ROM image file {}", file_name);
println!("Reloaded ROM image file {file_name}");
} else {
println!("No ROM image file to reload");
}