diff --git a/src/disas.rs b/src/disas.rs index 11813f8..75c1edd 100644 --- a/src/disas.rs +++ b/src/disas.rs @@ -460,8 +460,8 @@ impl Disasm<'_, T> { Ok(Instruction::Trap(vector)) } else if ins_word[4..13].load_be::() == 0b1_1100_1010 { let areg = ins_word[13..16].load_be::(); - let displacement = self.read_immediate(Size::Word)? as u16; - Ok(Instruction::Link { areg, displacement }) + let displacement = self.read_immediate(Size::Word)? as i16; + Ok(Instruction::Link {areg, displacement}) } else if ins_word[4..13].load_be::() == 0b1_1100_1011 { let dst = ins_word[13..16].load_be::(); Ok(Instruction::Unlk(dst)) diff --git a/src/instruction.rs b/src/instruction.rs index 2516741..2e4f45f 100644 --- a/src/instruction.rs +++ b/src/instruction.rs @@ -334,7 +334,7 @@ pub enum Instruction { Trap(u8), Link { areg: u8, - displacement: u16, + displacement: i16, }, Unlk(u8), MoveUsp(MoveDirection, u8), @@ -475,7 +475,7 @@ impl Display for Instruction { Self::Tas(dst) => write!(f, "TAS {dst}"), Self::Tst(size, src) => write!(f, "TST.{size} {src}"), Self::Trap(vec) => write!(f, "TRAP #{vec:#x}"), - Self::Link { areg, displacement } => write!(f, "LINK A{areg}, #{displacement:#x}"), + Self::Link { areg, displacement } => write!(f, "LINK A{areg}, #{displacement}"), Self::Unlk(areg) => write!(f, "UNLK A{areg}"), Self::MoveUsp(dir, areg) => match dir { MoveDirection::MemToReg => write!(f, "MOVE USP, A{areg}"), diff --git a/src/m68k.rs b/src/m68k.rs index da2245a..adbdd1d 100644 --- a/src/m68k.rs +++ b/src/m68k.rs @@ -595,9 +595,14 @@ impl M68K { self.push(dst_val, Size::Long)?; let sp = self.read_effective(EffectiveAddress::AddressReg(7), Size::Long)?; self.write_effective(dst, sp, Size::Long)?; + let new_sp = if displacement >= 0 { + sp.wrapping_add(displacement as u32) + } else { + sp.wrapping_sub(-displacement as u32) + }; self.write_effective( EffectiveAddress::AddressReg(7), - sp.wrapping_add(u32::from(displacement)), + new_sp, Size::Long, )?; }