Finish basic functions of MMU card
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10
Cargo.lock
generated
10
Cargo.lock
generated
@ -73,15 +73,6 @@ version = "3.12.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "0d261e256854913907f67ed06efbc3338dfe6179796deefc1ff763fc1aee5535"
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[[package]]
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name = "card_macro"
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version = "0.1.0"
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dependencies = [
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"proc-macro2",
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"quote",
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"syn",
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]
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[[package]]
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name = "cc"
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version = "1.0.78"
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@ -521,7 +512,6 @@ dependencies = [
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"anyhow",
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"bitflags",
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"bitvec",
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"card_macro",
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"clap 3.2.23",
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"derive-try-from-primitive",
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"elf",
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@ -9,7 +9,6 @@ edition = "2021"
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anyhow = "1.0.66"
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bitflags = "1.3.2"
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bitvec = "1.0.0"
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card_macro = { version = "0.1.0", path = "card_macro" }
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clap = { version = "3.2.23", features = ["clap_derive", "derive"] }
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derive-try-from-primitive = "1.0.0"
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elf = "0.7.0"
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147
src/mmu.rs
147
src/mmu.rs
@ -4,7 +4,7 @@ use nullable_result::NullableResult;
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use crate::{
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backplane::{Backplane, CardAccessorBuilder, DMAHandler, MMUHandler},
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card::{u16_get_be_byte, Card},
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card::{u16_get_be_byte, u32_get_be_byte, u32_set_be_byte, Card},
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m68k::BusError,
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register,
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};
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@ -35,7 +35,10 @@ impl From<u32> for PagingEntry {
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pub struct MmuCard {
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enabled: bool,
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cache: [Option<PagingEntry>; 4096],
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map_frames: [Option<u32>; 4],
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map_frames: [u32; 4],
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map_frames_enabled: [bool; 4],
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tlb_clear_entry: u16,
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print_debug: bool,
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}
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impl Card for MmuCard {
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@ -44,7 +47,10 @@ impl Card for MmuCard {
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Self {
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enabled: false,
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cache: [None; 4096],
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map_frames: [None; 4],
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map_frames: [0; 4],
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map_frames_enabled: [false; 4],
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tlb_clear_entry: 0,
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print_debug: false,
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},
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None,
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))
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@ -56,14 +62,78 @@ impl Card for MmuCard {
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fn read_byte_io(&mut self, address: u8) -> NullableResult<u8, BusError> {
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match address {
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(0x0..=0xF) => {
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let map_no = (address / 4) as usize;
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let offset = address % 4;
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match offset {
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(0..=2) => NullableResult::Ok(u32_get_be_byte(self.map_frames[map_no], offset)),
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3 => NullableResult::Ok(self.map_frames_enabled[map_no] as u8),
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_ => unreachable!(),
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}
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}
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(0xFE..=0xFF) => NullableResult::Ok(u16_get_be_byte(ID, address - 0xFE)),
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_ => NullableResult::Null,
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}
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}
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fn write_byte_io(&mut self, address: u8, data: u8) -> NullableResult<(), BusError> {
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match address {
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(0x0..=0xF) => {
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let map_no = (address / 4) as usize;
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let offset = address % 4;
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match offset {
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(0..=1) => {
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self.map_frames[map_no] =
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u32_set_be_byte(self.map_frames[map_no], offset, data);
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}
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2 => {
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self.map_frames[map_no] =
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u32_set_be_byte(self.map_frames[map_no], offset, data & 0xf0);
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}
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3 => {
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self.map_frames_enabled[map_no] = (data & 0x1) > 0;
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for i in map_no * 1024..(map_no + 1) * 1024 {
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self.cache[i] = None;
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}
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}
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_ => unreachable!(),
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};
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}
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(0x10..=0x13) => {
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let offset = (address - 0x10) % 4;
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match offset {
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0 => (),
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1 => {
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self.tlb_clear_entry = (self.tlb_clear_entry & 0xF) | ((data as u16) << 4);
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}
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2 => {
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self.tlb_clear_entry =
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(self.tlb_clear_entry & 0xFF0) | (((data as u16) & 0xF0) >> 4);
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}
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3 => {
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if self.print_debug {
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println!(
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"Clearing TLB entry {:#x} ( page start {:#x} )",
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self.tlb_clear_entry,
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(self.tlb_clear_entry as u32) << 12
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);
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}
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self.cache[self.tlb_clear_entry as usize] = None;
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}
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_ => unreachable!(),
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}
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}
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0x15 => {
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self.enabled = (data & 0x1) > 0;
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}
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_ => (),
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}
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NullableResult::Ok(())
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}
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fn cmd(&mut self, cmd: &[&str]) -> anyhow::Result<()> {
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if cmd[0] == "enable" && cmd.len() >= 2 {
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self.enabled = cmd[1].parse()?;
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if cmd[0] == "debug" && cmd.len() >= 2 {
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self.print_debug = cmd[1].parse()?;
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}
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Ok(())
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}
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@ -75,9 +145,33 @@ impl Card for MmuCard {
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impl Display for MmuCard {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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let q1 = if self.map_frames_enabled[0] {
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Some(self.map_frames[0])
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} else {
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None
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};
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let q2 = if self.map_frames_enabled[1] {
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Some(self.map_frames[1])
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} else {
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None
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};
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let q3 = if self.map_frames_enabled[2] {
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Some(self.map_frames[2])
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} else {
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None
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};
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let q4 = if self.map_frames_enabled[3] {
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Some(self.map_frames[3])
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} else {
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None
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};
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f.write_fmt(format_args!(
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"MMU card, {}",
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"MMU card, {} (Q1: {:?}, Q2: {:?}, Q3: {:?}, Q4: {:?})",
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if self.enabled { "enabled" } else { "disabled" },
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q1,
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q2,
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q3,
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q4
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))
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}
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}
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@ -94,26 +188,59 @@ impl MMUHandler for Mmu {
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write: bool,
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) -> NullableResult<u32, BusError> {
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let card_accessor = card_accessor.build::<MmuCard>();
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if card_accessor.get().enabled {
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let card = card_accessor.get();
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let print_debug = card.print_debug;
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if card.enabled {
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let page = address >> 12;
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let offset = address & 0xFFF;
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let entry = if let Some(entry) = card_accessor.get().cache[page as usize] {
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let entry = if let Some(entry) = card.cache[page as usize] {
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if print_debug {
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println!("TLB hit");
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}
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entry
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} else {
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let map_frame = card_accessor.get().map_frames[(page >> 10) as usize]?;
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let entry_address = (map_frame << 12) | ((page & 0x3FF) << 2);
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if print_debug {
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println!("TLB miss, fetching entry");
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}
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if card.map_frames_enabled[(page >> 10) as usize] == false {
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if print_debug {
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println!("No mapping frame for this quarter");
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}
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return NullableResult::Null;
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}
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let map_frame = card.map_frames[(page >> 10) as usize];
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let entry_address = (map_frame) | ((page & 0x3FF) << 2);
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if print_debug {
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println!("Entry is at {:#x}", entry_address);
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}
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drop(card);
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let entry_hi = backplane.read_word_phys(entry_address)?;
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let entry_lo = backplane.read_word_phys(entry_address + 2)?;
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let entry = PagingEntry::from((entry_hi as u32) << 16 | entry_lo as u32);
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card_accessor.get().cache[page as usize] = Some(entry);
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if print_debug {
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println!("Fetched entry {:#?}", entry);
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}
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entry
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};
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if entry.present {
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if write && !entry.writable {
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if print_debug {
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println!("Entry not writable");
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}
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return NullableResult::Err(BusError);
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}
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if print_debug {
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println!(
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"Translation success, translated to {:#x}",
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(entry.frame << 12) | offset
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);
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}
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NullableResult::Ok((entry.frame << 12) | offset)
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} else {
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if print_debug {
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println!("Entry not present");
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}
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NullableResult::Null
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}
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} else {
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