diff --git a/src/disas.rs b/src/disas.rs
index 09d8ffa..4f530f0 100644
--- a/src/disas.rs
+++ b/src/disas.rs
@@ -22,10 +22,12 @@ enum InstructionCategory {
     Moveq = 7,
     OrDivSbcd = 8,
     SubSubx = 9,
+    Unimp10 = 10,
     CmpEor = 11,
     AndMulAbcdExg = 12,
     AddAddx = 13,
     ShiftRotate = 14,
+    Unimp15 = 15,
 }
 
 #[derive(TryFromPrimitive, Debug, Copy, Clone, PartialEq, Eq)]
@@ -228,6 +230,8 @@ impl<T> Disasm<'_, T> {
                 2 => Size::Long,
                 _ => unreachable!(),
             },
+            // Dummy size for unimplemented instructions
+            InstructionCategory::Unimp10 |InstructionCategory::Unimp15 => Size::Long,
         };
         match category {
             InstructionCategory::BitMovepImmed => {
@@ -881,6 +885,8 @@ impl<T> Disasm<'_, T> {
                 };
                 Ok(Instruction::Shift(op, size, dir, rotation, dst))
             }
+            InstructionCategory::Unimp10 => Ok(Instruction::Unimp10),
+            InstructionCategory::Unimp15 => Ok(Instruction::Unimp15),
         }
     }
 
diff --git a/src/instruction.rs b/src/instruction.rs
index 91860f6..ba7f4b3 100644
--- a/src/instruction.rs
+++ b/src/instruction.rs
@@ -423,6 +423,8 @@ pub enum Instruction {
     },
     Adda(u8, Size, EffectiveAddress),
     Shift(ShiftType, Size, ShiftDirection, Rotation, EffectiveAddress),
+    Unimp10,
+    Unimp15,
 }
 
 impl Display for Instruction {
@@ -546,6 +548,8 @@ impl Display for Instruction {
                     _ => write!(f, "{dst}"),
                 }
             }
+            Self::Unimp10 => write!(f, "UNIMP10"),
+            Self::Unimp15 => write!(f, "UNIMP15"),
         }
     }
 }
diff --git a/src/m68k.rs b/src/m68k.rs
index 8058d68..dfaa9e5 100644
--- a/src/m68k.rs
+++ b/src/m68k.rs
@@ -1120,6 +1120,14 @@ impl M68K {
                     | u8::from(carry);
                 self.sr = self.sr & 0xFFE0 | u16::from(flags);
             }
+            Instruction::Unimp10 => {
+                self.trap(10)?;
+                return Err(InsExecError::AbnormalTrap);
+            }
+            Instruction::Unimp15 => {
+                self.trap(11)?;
+                return Err(InsExecError::AbnormalTrap);
+            }
         };
         Ok(())
     }