Revert "Rework MMU trait to allow for full control of MMU issued memory cycles"
This commit breaks accesses to the MMU IO space because since the MMU card is borrowed during accesses to memory, when it calls into the backplane to do the physical access, the backplane will attemp to borrow the MMU card again, causing a panic
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3a4d2b0c9d
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8f91a1aa3e
GPG Key ID:
7B5F6AFBEC7EE78E
@ -148,51 +148,43 @@ impl Backplane {
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}
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pub fn read_word(&self, address: u32) -> Result<u16, BusError> {
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if let Some(mmu) = self.mmu {
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self.cards[mmu]
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.borrow_mut()
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.try_as_mmu()
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.unwrap()
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.read_word(address, self)
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} else {
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self.read_word_phys(address)
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}
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self.mem_helper(
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address,
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|mut card| card.read_word(address),
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|mut card| card.read_word_io(address as u8),
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false,
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false,
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)
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}
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pub fn read_byte(&self, address: u32) -> Result<u8, BusError> {
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if let Some(mmu) = self.mmu {
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self.cards[mmu]
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.borrow_mut()
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.try_as_mmu()
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.unwrap()
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.read_byte(address, self)
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} else {
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self.read_byte_phys(address)
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}
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self.mem_helper(
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address,
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|mut card| card.read_byte(address),
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|mut card| card.read_byte_io(address as u8),
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false,
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false,
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)
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}
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pub fn write_word(&self, address: u32, data: u16) -> Result<(), BusError> {
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if let Some(mmu) = self.mmu {
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self.cards[mmu]
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.borrow_mut()
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.try_as_mmu()
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.unwrap()
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.write_word(address, data, self)
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} else {
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self.write_word_phys(address, data)
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}
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self.mem_helper(
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address,
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|mut card| card.write_word(address, data),
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|mut card| card.write_word_io(address as u8, data),
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false,
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true,
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)
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}
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pub fn write_byte(&self, address: u32, data: u8) -> Result<(), BusError> {
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if let Some(mmu) = self.mmu {
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self.cards[mmu]
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.borrow_mut()
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.try_as_mmu()
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.unwrap()
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.write_byte(address, data, self)
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} else {
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self.write_byte_phys(address, data)
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}
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self.mem_helper(
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address,
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|mut card| card.write_byte(address, data),
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|mut card| card.write_byte_io(address as u8, data),
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false,
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true,
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)
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}
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pub fn read_word_phys(&self, address: u32) -> Result<u16, BusError> {
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@ -200,30 +192,41 @@ impl Backplane {
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address,
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|mut card| card.read_word(address),
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|mut card| card.read_word_io(address as u8),
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true,
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false,
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)
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}
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#[allow(dead_code)]
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pub fn read_byte_phys(&self, address: u32) -> Result<u8, BusError> {
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self.mem_helper(
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address,
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|mut card| card.read_byte(address),
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|mut card| card.read_byte_io(address as u8),
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true,
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false,
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)
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}
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#[allow(dead_code)]
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pub fn write_word_phys(&self, address: u32, data: u16) -> Result<(), BusError> {
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self.mem_helper(
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address,
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|mut card| card.write_word(address, data),
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|mut card| card.write_word_io(address as u8, data),
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true,
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true,
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)
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}
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#[allow(dead_code)]
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pub fn write_byte_phys(&self, address: u32, data: u8) -> Result<(), BusError> {
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self.mem_helper(
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address,
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|mut card| card.write_byte(address, data),
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|mut card| card.write_byte_io(address as u8, data),
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true,
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true,
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)
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}
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@ -232,11 +235,29 @@ impl Backplane {
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address: u32,
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mut mem_func: M,
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mut io_func: I,
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bypass_mmu: bool,
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write: bool,
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) -> Result<T, BusError>
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where
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M: FnMut(RefMut<'_, dyn Card>) -> NullableResult<T, BusError>,
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I: FnMut(RefMut<'_, dyn Card>) -> NullableResult<T, BusError>,
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{
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let address = if bypass_mmu {
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address
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} else if let Some(card_no) = self.mmu {
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match self.cards[card_no]
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.borrow_mut()
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.try_as_mmu()
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.unwrap()
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.translate_address(self, address, write)
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{
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NullableResult::Ok(address) => address,
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NullableResult::Err(e) => return Err(e),
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NullableResult::Null => return Err(BusError),
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}
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} else {
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address
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};
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let res = match address {
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(0..=0x00fe_ffff) | (0x0100_0000..=0xffff_ffff) => self
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.cards
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15
src/card.rs
15
src/card.rs
@ -141,20 +141,15 @@ pub trait Card: Debug + Display + mopa::Any {
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mopafy!(Card);
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pub trait Mmu: Debug {
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fn read_word(&mut self, address: u32, backplane: &Backplane) -> Result<u16, BusError>;
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fn read_byte(&mut self, address: u32, backplane: &Backplane) -> Result<u8, BusError>;
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fn write_word(
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fn translate_address(
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&mut self,
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address: u32,
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data: u16,
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backplane: &Backplane,
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) -> Result<(), BusError>;
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fn write_byte(&mut self, address: u32, data: u8, backplane: &Backplane)
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-> Result<(), BusError>;
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address: u32,
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write: bool,
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) -> NullableResult<u32, BusError>;
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}
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#[allow(dead_code)]
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pub const fn u64_set_be_byte(val: u64, idx: u8, byte: u8) -> u64 {
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let mut bytes = val.to_be_bytes();
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48
src/mmu.rs
48
src/mmu.rs
@ -173,13 +173,13 @@ impl Display for MmuCard {
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}
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}
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impl MmuCard {
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impl Mmu for MmuCard {
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fn translate_address(
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&mut self,
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address: u32,
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backplane: &Backplane,
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address: u32,
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write: bool,
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) -> Result<u32, BusError> {
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) -> NullableResult<u32, BusError> {
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let print_debug = self.print_debug;
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if self.enabled {
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let page = address >> 12;
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@ -197,7 +197,7 @@ impl MmuCard {
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if print_debug {
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println!("No mapping frame for this quarter");
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}
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return Err(BusError);
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return NullableResult::Null;
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}
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let map_frame = self.map_frames[(page >> 10) as usize];
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let entry_address = (map_frame) | ((page & 0x3FF) << 2);
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@ -218,7 +218,7 @@ impl MmuCard {
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if print_debug {
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println!("Entry not writable");
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}
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return Err(BusError);
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return NullableResult::Err(BusError);
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}
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if print_debug {
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println!(
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@ -226,49 +226,17 @@ impl MmuCard {
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(entry.frame << 12) | offset
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);
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}
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Ok((entry.frame << 12) | offset)
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NullableResult::Ok((entry.frame << 12) | offset)
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} else {
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if print_debug {
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println!("Entry not present");
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}
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Err(BusError)
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NullableResult::Null
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}
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} else {
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Ok(address)
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NullableResult::Ok(address)
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}
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}
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}
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impl Mmu for MmuCard {
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fn read_word(&mut self, address: u32, backplane: &Backplane) -> Result<u16, BusError> {
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let address = self.translate_address(address, backplane, false)?;
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backplane.read_word_phys(address)
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}
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fn read_byte(&mut self, address: u32, backplane: &Backplane) -> Result<u8, BusError> {
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let address = self.translate_address(address, backplane, false)?;
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backplane.read_byte_phys(address)
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}
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fn write_word(
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&mut self,
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address: u32,
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data: u16,
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backplane: &Backplane,
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) -> Result<(), BusError> {
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let address = self.translate_address(address, backplane, true)?;
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backplane.write_word_phys(address, data)
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}
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fn write_byte(
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&mut self,
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address: u32,
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data: u8,
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backplane: &Backplane,
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) -> Result<(), BusError> {
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let address = self.translate_address(address, backplane, true)?;
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backplane.write_byte_phys(address, data)
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}
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}
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register!(MmuCard, "mmu");
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