Allow dissasembly errors to include abnormal traps
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parent
849f3c7dd2
commit
030ca22812
24
src/m68k.rs
24
src/m68k.rs
@ -144,8 +144,14 @@ impl From<DetailedBusError> for InsExecError {
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}
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}
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impl Display for InsExecError {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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match self {
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InsExecError::BusError(err) => f.write_fmt(format_args!("{}", err)),
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InsExecError::AbnormalTrap => f.write_str("Abnormal trap"),
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}
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}
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}
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#[derive(Debug)]
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pub struct M68K {
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@ -243,11 +249,14 @@ impl M68K {
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pub fn disassemble(
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&mut self,
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loc: u32,
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) -> Result<(Instruction, u32), DisassemblyError<DetailedBusError>> {
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) -> Result<(Instruction, u32), DisassemblyError<InsExecError>> {
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disas::disasm(loc, &mut |addr| {
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self.read_word(addr).map_err(|err| DetailedBusError {
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self.read_word(addr).map_err(|err| match err {
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InsExecError::AbnormalTrap => InsExecError::AbnormalTrap,
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InsExecError::BusError(err) => InsExecError::BusError(DetailedBusError {
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cause: BusErrorCause::ReadingInstruction,
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..err.try_into_bus_error().unwrap()
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..err
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}),
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})
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})
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}
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@ -316,7 +325,10 @@ impl M68K {
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}
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let (ins, new_pc) = match self.disassemble(self.pc) {
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Ok(ins) => ins,
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Err(DisassemblyError::InvalidInstruction) => panic!("Invalid instruction"),
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Err(DisassemblyError::InvalidInstruction) => {
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self.trap(4)?;
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return self.step_ret_berr();
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}
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Err(DisassemblyError::ReadError(e)) => return Err(e.into()),
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};
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self.pc = new_pc;
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@ -25,6 +25,7 @@ use clap::Parser;
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use disas::DisassemblyError;
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use indexmap::IndexSet;
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use itertools::Itertools;
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use m68k::InsExecError;
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use parse_int::parse;
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use reedline_repl_rs::{
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clap::{builder::BoolishValueParser, Arg, ArgAction, Command},
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@ -527,7 +528,7 @@ fn disas_fmt(
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cpu: &mut M68K,
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addr: u32,
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symbol_tables: &SymbolTables,
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) -> (String, Result<u32, DisassemblyError<DetailedBusError>>) {
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) -> (String, Result<u32, DisassemblyError<InsExecError>>) {
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let addr_fmt = if let Some((table, symbol, offset)) = symbol_tables.address_to_symbol(addr) {
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format!("{table}:{symbol} + {offset} (0x{addr:x})")
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} else {
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